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Vivado Design Suite improves plug-and-play IP integration

25 Oct 2013

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Xilinx has introduced the Vivado Design Suite 2013.3, which supports the UltraFast design methodology and improves configuration, integration and verification of plug-and-play IP, and partial reconfiguration. The Vivado Design Suite is co-optimised with Xilinx's all-programmable devices and is an SoC-strength design suite able to address the productivity bottlenecks in system-level integration and implementation.

To enable accelerated and predictable design cycles, Vivado Design Suite 2013.3 provides built-in automation of critical aspects of the UltraFast design methodology, providing design rule checks (DRC) guiding engineers throughout the design cycle and HDL and constraints templates enabling optimal quality of results.

Xilinx's plug-and-play IP initiative, introduced in 2012, leverages industry standards such as IP-XACT, IEEE P1735 encryption, and the AMBA AXI4 interconnect protocol to accelerate integration of IP. Earlier this year, the Vivado Design Suite changed the RTL design productivity plateau through its plug-and-play IP integration design environment with IP Integrator capability.

The Vivado Design Suite 2013.3 offers enhanced IP integration and more than 230 LogiCORE and SmartCORE IP cores. This release upgrade allows for system-wide co-optimisation of a design and Xilinx IP. For instance, designers can now share clocking resources throughout their design with connectivity IP such as Ethernet MAC or PCIe. Upgrades to the IP also provide access to transceiver debug ports within the IP. With new capabilities to the Vivado logic analyser, designers have full read-and-write access to their AXI system at runtime. They can also perform hardware debug using advanced trigger feature to detect and capture complex events.

This release also facilitates the IP integration through revision control systems and automates the verification flows with the Cadence Incisive Enterprise simulator and the Synopsys VCS simulator.

The Vivado Design Suite 2013.3 introduces support for partial reconfiguration, which has been used by many customers with the ISE Design Suite. This technology enables usage of device resources by swapping functions on demand. Partial reconfiguration can also result in lower power consumption and can enable field updates with no system downtime.

"Utilising Xilinx's partial reconfiguration feature in Vivado for 7 series devices has empowered Trendium to achieve a successful system on chip architecture while simultaneously meeting our PCI Express requirements," said Stephen Frey, Firmware Engineering Manager at Trendium. "Partial reconfiguration has allowed us to more efficiently utilise Xilinx silicon by interchanging protocol analysis modules for our network access agent platform without disrupting the PCI Express link. This approach also provides a path to upgrade the existing hardware with new modules for future product enhancements."




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