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RTL Compiler 13.1 boosts physically aware functions

22 Nov 2013

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Cadence Design Systems has unveiled version 13.1 of its Encounter RTL Compiler, which features new programs for physically aware capabilities. Promising 15 per cent better power efficiency, this latest RTL Compiler model can improve silicon results by allowing engineers to use physical aware techniques at the earliest phases of synthesis. The Encounter RTL Compiler 13.1 has already received positive feedback from Fujitsu Semiconductor America, which recently adopted the technology.

As geometries shrink beyond 28nm, changes in interconnect characteristics make it much more difficult to achieve optimal timing and closure. The new RTL Compiler capabilities let design teams address these challenges earlier in the design process so they can achieve faster timing closure, while improving performance, power and area.

Features of the new RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test that offer significant benefits for Cadence customers. Physically aware structuring and mapping can improve performance by more than 10 per cent and area by more than 15 per cent on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesise to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10 per cent by merging single registers into multi-bit registers that share a clock.

"Cadence has re-architected RTL Compiler to weave physical awareness into stages of RTL synthesis that were traditionally logic only, allowing engineers to leverage floorplan and placement data as early as possible in the flow to ensure correlation with the Encounter Digital Implementation System," said Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence.

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