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RTL synthesis requirements for sub-20nm designs

20 Feb 2014  | David Stratman, Sanjiv Taneja

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The small world of sub-20nm design has already dawned and has brought a new set of challenges for register-transfer level (RTL) designers as the race for best performance, power, and area (PPA) continues unabated. Challenges include giga-scale integration of new functionality; new physics effects; new device structures such as FinFETs, multi-Vt and multi-channel devices; interconnect stacks with vastly varying resistance characteristics between the top and bottom layers; and process variation.

These challenges are raising several questions. For example, can RTL synthesis handle giga-scale, giga-hertz designs in a timeframe of market relevance? Can logic synthesis perform accurate and predictive modelling of the interconnect stack and the physical effects in RTL? How do new device structures affect dynamic and leakage power trade-off and library choices? This paper will explore these challenges and provide an overview of state-of-the-art technology to address them in a predictable and convergent design flow.

The interconnect challenge
The fundamental development requirement for interconnects is to meet the high-speed transmission needs of global/local signals of chips, despite further scaling of feature sizes. As illustrated in figure 1, the total interconnect length in 20nm is 6000m in one square-centimeter of the chip area, representing a 2x increase over that of 32nm and over 3x increase over that of 65nm.

Figure 1: The total interconnect length in 20nm is 6000m in one square-centimeter of the chip area.

It is no surprise that the "interconnect/gate delay gap" continues to widen with the interconnect delay increasingly determining the chip performance (figure 2). The length of Metal 1 and the intermediate wires usually shrinks with traditional scaling, so any impact of their delay on performance is minimal. Boasting the longest wire lengths, global interconnects are likely to be impacted the most by the degraded delay. Materials changes or some amelioration of the copper (Cu) resistivity increase won't be enough to meet overall performance requirements. In figure 2, we can see the delay of Metal 1 and global wiring in future generations. One can integrate repeaters to address the delay in global wiring, but this approach comes with the trade-off of more power consumption as well as the need for increased chip area.

Figure 2: Above we can see the delay of Metal 1 and global wiring in future generations (Source: ITRS, 2011).

The use of heterogeneous multi-core systems is further exacerbating the interconnect challenge as interconnecting a large number of processor and GPU cores creates a large number of criss-crossing wires and spaghetti-like routing congestion.

Hierarchical scaling
High-performance processor cores rely on a large number of metal layers, applying a hierarchical wiring approach where the pitch and thickness at each conductor level is increased steadily to mitigate the performance impact of interconnect delay. From Cu wiring to low-k dielectrics, ASICs have many technology attributes in common with MPUs. Compared to MPU design, however, ASIC design methodology is generally more regular, with Metal 1, intermediate, semi-global (2x intermediate), and global (4x intermediate) wire pitches.

Interconnect stack and need for layer-aware optimisation
As depicted in figure 4, the interconnect resistance in advanced process nodes (20nm and beyond) can exhibit two orders of magnitude difference in the resistance values between lower and upper metal layers. The capacitance variation is relatively minor – note that the capacitance values increase for the upper layers, whereas the resistance values decrease. The delay calculation based on old assumptions about "layer-agnostic" delay calculation and optimisation breaks down. As a result, the synthesis tools need to evolve and consider at least multiple bins of the layer stacks based on the magnitude of the difference in resistance values, and use this information to drive layer-aware optimisation during synthesis.

Figure 3: These typical cross sections of hierarchical scaling show an MPU device (left) and an ASIC device (right).

Figure 4: This capacitance and resistance per layer data was generated by the Encounter RTL Compiler for typical advanced node library.

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