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Verific parser meets IEEE 1801-2013 requirements

17 Feb 2014

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Verific Design Automation has added features to its parser for the IEEE 1801-2013 standard for the design and verification of low-power integrated circuits, also called Universal Power Format 2.1 (UPF 2.1). The upgrade includes comprehensive error handler, maintenance of complete UPF descriptions, and easy integration with other data structures. The UPF 2.1 features are supported in the UPF parser. It conducts syntax and semantic checking, preserves all parameter values, and stores the UPF data in a parse tree for easy access. The UPF parser's comprehensive error handler maintains complete file, line, and column information on UPF descriptions.

An integral component of Verific's parser platform, the UPF parser interacts with Verific's standard SystemVerilog and VHDL parsers. It queries parse trees or netlists where applicable or, it can be queried from Verific's SystemVerilog or VHDL parse trees, or its netlist database. The UPF parser is also available stand-alone and can be integrated with external, or non-Verific, data structures.

The IEEE 1801-2013 UPF 2.1 standard, originally developed by standards organisation Accellera, is supported by multiple electronic design automation (EDA) vendors, many of whom are Verific customers. It provides a hardware description language independent way of annotating a design with power intent. It defines how to create supply networks to supply power to each design element using a set of commands.

"In a short period, UPF has become an important standard for describing low-power design and support is a priority for us," remarks Michiel Ligthart, Verific's president and chief operating officer.

Verific's software is the front end to a variety of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation, and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL, and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32bit and 64bit Unix, Linux, and Windows operating systems.

Verific will exhibit in Booth #805 during DVCon on Monday, March 3, from 5 p.m. until 7 p.m., and Tuesday and Wednesday, March 4 to 5, from 2:30 p.m. until 6 p.m. DVCon will be held at the DoubleTree Hotel in San Jose, Calif.




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