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Imagination merges visualisation with MCU-class processor

27 Feb 2014

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Imagination Technologies rolled out what it claims as the world's first MCU-class CPU IP cores that incorporate hardware virtualisation. The MIPS M-class M51xx cores form the first group of entry-level MIPS Series5 Warrior CPUs, achieving the highest CoreMark/MHz scores for MCU-class processors. The M51xx cores are ideal for industrial control, Internet of Things (IoT), wearables, cloud computing, wireless communications, automotive, storage and other applications.

The first available M-class cores are the M5100 and the M5150. The M5100 integrates a real-time execution unit and SRAM controller, and is optimised for low-cost, low-power microcontroller applications. The M5150 incorporates the same execution unit as the M5100 and adds a programmable L1 instruction and data cache controller, as well as memory management support for Linux and RTOS embedded system applications.

As with other MIPS Series5 cores, the M-class cores implement the MIPS Release 5 architecture incorporating hardware virtualisation. The M51xx cores are based on the same 5-stage pipeline architecture and leverage the high performance, comprehensive digital signal processing (DSP)/SIMD features of the previous generation MIPS microAptiv family of cores, along with the microMIPS Instruction Set Architecture (ISA) which provides up to 30 per cent code size reduction over 32bit only code.

Virtualisation: anticipating the needs of future

The addition of hardware virtualisation to MCU-class cores provides increased security and reliability for a wide range of applications. Based on feedback from numerous partners, Imagination believes the need for virtualisation is growing from the low end to the high end. This is why the entire line-up of Imagination's MIPS Series5 Warrior cores, including the entry-level M-class, the mid-range I-class and the high-end P-class cores, all incorporate hardware virtualisation technology.

With virtualisation, multiple, unmodified, operating systems and applications can run independently and securely at the same time on a single, trusted platform. This delivers a range of benefits for system development, including ability to execute multiple tasks in isolation, intelligent resource allocation across several guests secure downloads/uploads and?IP protection.

Built-in prioritisation mechanisms in the MIPS virtualisation architecture, with support for up to seven secure/non-secure guests, enable it to optimally support real-time functionality.

In space-constrained, low-power systems such as IoT or wearable devices, virtualisation could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another guest, under RTOS control, can provide the multimedia capabilities of the system.

For applications that demand an even higher level of security, the new M-class cores include tamper resistant features that provide countermeasures to unwanted access to the processor operating state. A secure debug feature increases the benefit by preventing external debug probes from accessing and interrogating the core internals.

The new M51xx cores also feature a Floating Point Unit (FPU) option supporting both single and double precision instructions for improved control systems processing. The FPU is well-proven, having been implemented in high-end MIPS cores.

A broad range of development tools is already available for the M51xx cores, from Imagination and numerous companies across the MIPS embedded ecosystem, with additional support in development. This includes compilers from Mentor Graphics and Green Hills Software, as well as development boards and debug probes, plus Linux and various RTOSes including Imagination's MeOS.

In addition, several hypervisors for the M-class cores are either available or under development from Imagination and leading third party hypervisor developers, enabling customers to take full advantage of the hardware virtualisation features. This includes several open source hypervisors such as KVM, the Kernel-based Virtual Machine, and a microkernel hypervisor, both of which are available now for the M5150 core.




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