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Better caching leads to improved processor performance

04 Mar 2014

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In the paper presented last year, Kurian; his advisor Srini Devadas, the Edwin Sibley Webster Professor of Electrical Engineering and Computer Science at MIT; and Omer Khan, an assistant professor of electrical and computer engineering at the University of Connecticut and a former postdoc in Devadas' lab, presented a hardware design that mitigates that problem. When an application's working set exceeds the private-cache capacity, the MIT researchers' chip would simply split it up between the private cache and the LLC. Data stored in either place would stay put, no matter how recently it's been requested, preventing a lot of fruitless swapping.

Conversely, if two cores working on the same data are constantly communicating in order to keep their cached copies consistent, the chip would store the shared data at a single location in the LLC. The cores would then take turns accessing the data, rather than clogging the network with updates.

The new paper examines the case where, to the contrary, two cores are working on the same data but communicating only infrequently. The LLC is usually treated as a single large memory bank: Data stored in it is stored only once. But physically, it's distributed across the chip in discrete chunks. Kurian, Devadas, and Khan have developed a second circuit that can treat these chunks, in effect, as extensions of the private cache. If two cores are working on the same data, each will receive its own copy in a nearby chunk of the LLC, enabling much faster data access.

The systems presented in both papers require active monitoring of the chips' operation, to determine, for instance, when working sets exceed some bound, or when multiple cores are accessing the same data. In each case, that monitoring requires a little extra circuitry, the equivalent of about five percent of the area of the LLC. But, Kurian argued, because transistors keep shrinking, and communication isn't keeping up, chip space is not as crucial a concern as minimizing data transfer. Kurian, Devadas and Khan are also working to combine the two monitoring circuits, so that a single chip could deploy the cache-management strategies reported in both papers.

"It is a great piece of work," said Nikos Hardavellas, an assistant professor of electrical engineering and computer science at Northwestern University. "It definitely moves the state of the art forward." Existing caching schemes, Hardavellas explained, do treat different types of data differently: They might, for instance, use different caching strategies for program instructions and file data. "But if you dig deeper into these categories, you see that the data can behave very differently. In the past, we didn't know how to efficiently monitor the usefulness of the data. The [new] hardware design allows us to do this. That's a significant part of the contribution."

Moreover, Hardavellas said, "the two different designs seem to be working synergistically, which would indicate that the final result of combining the two would be better than the sum of the individual parts." As for commercialization of the technology, "I see no fundamental reason why not to. They seem implementable, they seem small enough, and they give us a significant benefit."

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