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32bit MCU core adds streaming instruction

12 Mar 2014  | Nick Flaherty

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FTDI has revealed that the architecture of its 32bit MCU core has a dedicated streaming instruction for data to avoid interrupts. The proprietary streaming architecture found at the FT900 claims to offer a highly efficient data transport mechanism that the company said is far more effective and less cumbersome than conventional memory-move instructions or DMA architecture implementations.

This streaming mechanism is composed of a single 32bit instruction set that enables rapid data movement to be carried out to and from the memory to the connected peripherals. It contains source, destination and size information within the instruction set. In addition, due to the vast peripheral support contained within the microcontroller, the streaming mechanism also provides different data width support (8, 16 and 32bit) in the single instruction.

Building on the streaming architecture, each peripheral contains a limited memory to expedite faster data transport when the instruction is executed. The basic principal of this architecture is to reduce the overhead, so that when streaming is activated, the processor core performs at very high rates without any hardware or software interrupting. So, for example, if 64 bytes worth of data need to be moved from a particular USB endpoint to a particular memory location, a single instruction will be sufficient to execute the data transport.

In contrast to a DMA architecture or a memory-move instruction, the overhead needed to manage the transfer process is considerably less. In most cases, the interrupt mechanism can be used to inform processor that the block of data transfer has been completed. Thanks to the streaming architecture, the inclusion of DMA-to-processor blocks can be avoided, so that computational results are streamed directly to the designated end point, resulting in zero wait state operation and higher data throughput in less clock cycles. The architecture eliminates the need to add overhead to take care of the interrupt routine leading to much faster data transport in a more controlled manner.

As a result the FT900 with its streaming architecture and targeted instruction set achieves Dhrystone MIPS (DMIPS) benchmarks well above similar 32bit architectures.

The controller is designed to be combined with FTDI Chips highly integrated Embedded Video Engine (EVE) graphic controller technology to provide a streamlined remote, local, or network monitoring system for home security, commercial surveillance and industrial control implementations. This is where FTDI believes the architecture can take on existing 32bit chips such as ARM and MIPS, using an Eclipse-based development system and low cost GNU compiler.

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