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Resolving FPGA board design challenges

20 Mar 2014  | Michael Dunn

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Here's when the "gotchas" can start to appear:

 • Do a thermal analysis, and add a heatsink if necessary.
 • Does the FPGA require power sequencing? (your design might easily need five or six supply voltages)
 • At least one "quiet" supply will probably be needed, usually for on-chip PLLs. Use an LDO plus some passive filtering. Gigabit transceiver power can also benefit from low-noise.
 • Make sure you understand what the FPGA does during power-up & initialisation. Many parts draw heavy current.

Of pins and things
You're ready to get down to the nitty-gritty of pin assignments. Once again, if your logic design is at a stage where it can be compiled, let the design software help out here, or at least verify your assigned pinning is feasible before hitting the board shop. You've of course handled the obvious stuff, like partitioning up the I/O banks by supply voltage, and making sure "special" pin settings like LVDS, SSTL, or internal 50Ω terminations are compatible with their chosen bank and supply voltage.

But there's a deeper level of subtlety lurking in many parts: complicated rules along the lines of "do not place a differential pair within 2 IC bonding pads of a single-ended signal," or "an input which is compared to a reference voltage must be at least 3 pads away from a clock signal." It's enough to drive one batty. If it all sounds unbearable, let the design software point out violations for you. If you don't, they will surely come back to getcha.

Ground bounce, or SSN (simultaneous switching noise), is yet another consideration. Since there are so many ways to apply an FPGA, vendors often design power distribution for best-case scenarios. If your design pushes the I/O's capabilities, say by using large numbers of fast, simultaneously switching outputs, you may need to "derate" the number of pins that can actually be used. Minimising drive and slew settings is always a good idea. The design software may be able to help out with SSN analysis too. One trick I've considered to reduce SSN is to tie unused pins to ground, then actually set them to outputs in your design file, driving '0'. These will act as pseudo ground pins, albeit not as good quality as the real ones.

The handoff
It's time to hand off the product of your blood, sweat, and tears to PCB layout. I won't delve into PCB design here, but will point out a few things to think about for FPGA designs.

Stackup design is critical to any complex board, and FPGAs are usually found on the most complex of them. With 500-pin chips being considered "mid-range", and ever-shrinking pitch, you'll be paying plenty of attention to trace escape patterns, via-in-pad, decoupling caps in the pin field, and power & ground planes. Be creative. Break up power planes if it helps (avoiding high-speed traces of course). With care, some power connections (typically localized ones like the PLL supply) can be made on signal layers. Put key planes and signals on layers closest to the FPGA. Heed special layout recommendations, such as those for DRAM.

If you've assiduously read user manuals, datasheets, and appnotes – if you've paid attention to every crossed 't' and dotted 'i' – there's a good chance your board will work, first time. Remember, assume nothing. Read everything. Twice. Ask your FAE. Ask here. Attend conferences where you can learn from and quiz experts in the field, and share knowledge with your peers. Good luck!

About the author
Michael Dunn has been messing with electronics almost as long as he's been walking, and got his first scope around age 15. Things have gone downhill since then. The scopes now vie with wine racks, harpsichords, calculators, and 19th century pianos for space. Over the years, he's designed for the automotive, medical, industrial, communications, and consumer industries, as both freelancer and employee, working with analogue, digital, micros, and software. Since 2000, he's run the TekScopes Yahoogroup, now with over 5,000 members, and he was previously editor-in-chief of Scope Junction.

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