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Sonics unveils SoC performance profile and debug IP

20 Mar 2014

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Sonics Inc. introduced Sonics Performance Monitor and Hardware Trace (SonicsMT), a semiconductor intellectual property (IP) product that accelerates the post-silicon system validation and software development processes for complex systems-on-chip (SoC). SonicsMT enables architects and software development teams to create SoC performance and debugging strategies that significantly shorten the time from silicon production to optimised working system.

"Today's SoCs contain multiple programmable processors and cores that generate a huge volume of transactions," said Ray Brinks, senior vice president of operations at Sonics. "SonicsMT provides SoC designers and software engineers the capability to visualise internal performance behaviours and tune system and software performance with pinpoint accuracy in a non-intrusive manner."

SonicsMT is automatically embedded inside the on-chip interconnect and leverages existing NoC infrastructure to minimise gate count while achieving real-time, at speed (within one clock cycle of the event) monitoring and tracing of the critical performance metrics.

It facilitates analysis and debug strategies for chip architecture exploration (performance and mode interactions, power usage, memory utilisation, traffic congestion for the current design as well as next-generation products), software development (driver and application debug, memory optimisation, algorithm development, power optimisation, hardware acceleration interactions) and chip services (performance guarantees, class of service monitoring).

SonicsMT visualises metrics such as burst density, read-write turnaround and other key characteristics of SoC traffic that influence overall system performance. The SoC designer defines design-time configuration parameters that precisely specify the requirements needed for each SonicsMT instance in the NoC. The designer also defines the trace packets that are of interest based on their knowledge of the application. Performance measurements and tracing are taken in "windows" that can automatically repeat for long debug runs which create histograms of the various metrics over time.

SonicsMT is compliant with the ARM CoreSight SoC architecture and easily integrates with this widely used SoC debug environment. It provides support for all CoreSight technology features including cross-triggering, authentication, global time stamps and topology detection. Users program SonicsMT via the CoreSight SoC Debug Access Point (DAP). It also enables debug support from third-party, CoreSight component compliant tools.

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