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Digital-analogue combined IP design, verification

09 Apr 2014  | Tejbal Prasad, Sachin Jain, Arun Barman

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The Glitch issue: At the RTL level, the design captures the values at clock edges only, so essentially any intermediate state of the combinational outputs are ignored and its value is registered at a specific edge of the clock only. The output of the combinational block changes its value until the effects of all the registered values used as inputs for the combinational logic are completely propagated though the combinational logic cones to generate the output. These produce glitches at the combinational output that should settle before the setup time of the registering/capturing flip-flop.

If the output of any combinational logic is used as the input of analogue circuit then glitches in the signal may produce undesired or sometimes catastrophic effects which may lead to either degradation of performance or accuracy, causing permanent damage to the analogue circuits. Hence it is very important to check the behaviour of the analogue circuit's input signals that control the internal functionality directly.

The behaviour of certain input signals must follow some specific pre-defined patterns without any glitch in-between to realise proper functionality of the analogue circuit, keeping its performance or accuracy as per specification without damaging the circuit.

This specific glitch issue at the output of the digital circuit must be ensured in design. There are certain cases where the signal behaviour required by analogue is such that it has to be driven from combinational logic only. In such cases there are guidelines as described below to avoid glitches.

Design guidelines to avoid glitch at digital output controlling analogue circuit
The signals propagating to the analogue block which toggle always at one type of clock edge (either positive or negative) shall be driven from a flip-flop only.

The signals which can toggle at both clock edges and can't be driven by a single flip-flop shall be driven by a combinational logic that takes inputs from flip-flops operating at different edges in a grey style manner w.r.t clock edges.

The signals which will never toggle during active period of operation of analogue circuit may be driven from combinational logic, but design implementation must ensure a glitch-less operation while the analogue circuit is active, i.e. the glitch, even if it occurs, will be during power-down or inactive period of analogue which can't cause any harm to the analogue circuit or performance.

Glitch at ADC capacitor's charging / discharging switch control (ccode*) destroys the charge in it thus degrades its performance.

The skew issue
In order for the analogue circuit to have better performance, its input control signals must have some correspondence amongst them in the time domain during changing their state. This puts a hard requirement to meet a defined skew margin among them while entering into the analogue circuit.

If the pattern of one signal doesn't come into correspondence with defined skew relative to the other signal then their overlapping pattern can lead to performance degradation or damage to the analogue circuit.

The variation of path delays and parasitic effects on the signal from digital to analogue contributes to the skew among the signals towards the analogue circuit.

Guidelines to avoid skew variation
The delays of signals from the active / launching clock edge until the analogue circuit boundary must be the same for all signals.

Synthesis tool shall put delay buffers in the path of fast reaching signals to match its delay w.r.t the late arriving signal.

The synthesis constraint and tool setting should be set to meet these delays during Placement & Routing.

Integration guide of the IP should cover the requirement of delays of each signal taking feedback from IP level synthesis reports.

Examples of issues with skew:
Delay variation between the capacitor switch controls of the ADC can lead to accuracy degradation.

Delay variation between the sample switch control and comparator enable control can lead to huge current in the analogue circuitry and may damage the analogue circuit elements.

The timing issue
The setup and hold time of sequential elements like a flip-flop in digital logic must be met to realise proper operation of IP without any failure. The inputs of the digital logic coming from the analogue circuit must come before the setup time of the capturing flip-flop.

The analogue circuit takes its own time to respond specified in terms of absolute time frame (ns, us etc.). There are certain cases that require that the analogue response must come within a clock cycle of the digital to generate the next cycle inputs of analogue from digital.

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