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Digital-analogue combined IP design, verification

09 Apr 2014  | Tejbal Prasad, Sachin Jain, Arun Barman

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This puts a hard requirement that the round trip path delay from the launching clock edge to the capturing clock edge which includes that the analogue response delay must meet the setup time of capturing flip-flop.

The total time required must be less than one clock cycle period of digital including the jitter, uncertainty, timing de-rate and other effects of clock.

Failure to meet the round-trip timing requirement leads to the wrong operation of digital and thus degradation of performance and/or malfunction of the IP.


Guidelines to avoid timing violation
The timing budget of all the worst / critical paths contributing in the generation of the analogue output must be done carefully along with analogue circuit requirements

During timing budget delay, other effects like skew matching, routing delay, clock to Q delay, jitter, uncertainty etc. must be taken into account


Timing model of the analogue block
During the synthesis of the digital logic, the analogue block is replaced with a timing model. This timing model contains the interface timing requirements between the digital and analogue block.

An accurate timing model is required to convey the exact timing requirement to the synthesis tool so that it can insert the necessary delay elements into the signal path to meet the skew and setup requirement.

The main challenge is to derive the timing requirements of the interface signals w.r.t the reference edges and reference signal. These are very tricky and need careful observation of the signal's pattern, so it becomes a bit difficult to model them accurately. The basic objective here is to meet the skew requirement among the signals and the setup.


Guidelines for the timing model
To meet the skew requirements in all Process, voltage and temperature (PVT) corners, one of the signals is taken as the clock and all others are timed with it. The choice of reference signal is done on the basis of minimum variation across PVTs. The signal with the least variation is chosen.

Data to data setup and hold checks need to be applied for rise-to-rise, fall-to-fall, rise-to-fall and fall-to-rise depending on timing requirements w.r.t the reference signal.

The timing model shall have to model the round trip delay as required for signals.


Scan coverage of interface logic and any digital logic inside analogue
During scan test for the digital part, the coverage of the interfacing logic is lost due to Non-Observability of its outputs which propagates inside analogue circuit. Thus any fault that occurs in this will remain undetected and will cause the failure of the IP without showing any reason.

So during the scan test mode there should be some means to observe the outputs of the digital that goes to analogue circuit.

The inputs of the digital from the analogue also floats during the scan test and thus makes things uncontrollable. This creates issues in the capture state. The captured value is not determined due to uncontrollability. Hence during the scan there should be some means to make the inputs controllable.


Guidelines for better scan coverage
The outputs towards the analogue block are XOR-ed in a tree structure to make one or more signals that are feed to the inputs coming from analogue during the scan mode of operation.

Multiplexers are put at the inputs coming from the analogue that selects the output of the XOR tree during the scan mode.


Challenges in verification of mixed-signal IPs
Functional Verification of these Mixed Signal blocks is quite tricky and requires a different set of infrastructure. In the subsequent sections we will discuss in detail the approach to handle such IPs in verification and the key requirements to efficiently sign them off.

Figure 2 shows a sample verification environment for a Mixed Signal block.


Figure 2: Mixed-signal IP verification environment.


In order to achieve a highly configurable and randomized verification environment, the following are the essential components of the Testbench:

Register Interface Driver: This is a driver that allows programming the digital register programming model in order to configure the IP and to extract the data from the analogue system.

Analogue Behavioural model (Verilog AMS): In order to efficiently verify the analogue component, an accurate behavioural model representing the analogue functionality is required. A simple Verilog model is not enough, since it does not allow modelling of all analogue characteristics. On the other hand, using a spice model – although it represents analogue characteristics quite accurately—is also not recommended, since it is very time consuming to run simulations.

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