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Digital-analogue combined IP design, verification

09 Apr 2014  | Tejbal Prasad, Sachin Jain, Arun Barman

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A middle path is to use the Verilog-AMS (VAMS) based models. This model allows modelling of all the complex analogue characteristics and functionality while not consuming too much simulation time. Although it is less accurate than SPICE, but for faster functional verification it best serves the purpose.

VAMS Driver: In order to use the VMAS model of the analogue IP – which models analogue characteristics like voltage and current – we also need a set of drivers that can drive values on these VAMS models. The drivers in Testbench generate these analogue signals.

Scoreboard/Monitors: Scoreboard and Monitors are elements that ensure protocol and data checks within the Testbench. In general the scoreboard includes the model of the transfer function to be able to do exhaustive random verification of data over the input and output.

Randomisation of analogue signals: In order to ensure robust verification at the IP level, it needs to be ensured that each and every function inside the analogue model is exercised thoroughly. Since we are dealing with analogue models, there is a need to have a control on these analogue quantities.

In the verification environment, electrical signals are represented by real numbers. System Verilog does not allow randomizing real numbers easily, so to randomise this real number, the desired analogue voltage range (0-5V, 0-3.3V or 0-1.2V) is divided into X, where X is the desired resolution (8bit, 16bit, 32bit or 64bit). The higher is the resolution, the slower are the simulations.

The code snippet below shows how to randomise the real number:

rand int P_CH_V_val_x100000;
real P_CH_V_real_x100000;
real P_CH_V_real;
constraint channel_voltage_range_P1 {P_CH_V_val_x100000 inside {[0:MAX_V_x100000]}; }

P_CH_V_real_x100000 = P_CH_V_val_x100000;
P_CH_V_real = P_CH_V_real_x100000 / 100000;

The code snippet below shows the modification needed to hook up the same in the VAMS driver:

output V_out;
electrical V_out;

analogue begin
V(V_out,gnd_node) <+ transition(P_CH_V_real,10p,100p);
end


Challenges
Some of the challenges in designing the above verification environments and approach are discussed below.

The VAMS model used has to be synced with the analogue views at all times during the design cycle. If there is any defect that is fixed on the analogue view, then the same has to be updated in the VAMS model as well. There are today no tools available to prove logical equivalence between the VAMS models and Spice netlists.

This VAMS-based simulations are not accurate and are used only for functional correctness and early interoperability of the Digital-analogue logic.

As soon as you start increasing the resolution (by using higher size variables), the simulation starts slowing down.


Summary
Mixed Signal IPs are tricky and require special care both in design and verification. There are various design considerations that need to be taken while designing these IPs. Verification of these IPs is equally challenging. With the advancements in the EDA tools and methodologies, it has become quite easy and faster to be able to model such test benches efficiently. Mixed Signal Simulation is an efficient way to verify mixed signal IPs efficiently. This not only enables us to verify the functional correctness of these IPs quickly but also with reasonable accuracy.


About the authors
Tejbal Prasad is lead verification engineer in IP verification team at Freescale Semiconductors India.

Sachin Jain is a Design Manager with the Automotive and Industrial Solutions Group at Freescale.

Arun Barman also contributed to this article.

To download the PDF version of this article, click here.


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