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Sony, TSMC optimise image sensors

10 Apr 2014  | Peter Clarke

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Image sensors will take the limelight at an upcoming engineering conference where two papers are set to be presented.

Sony Corp. is due to report on an improved CMOS image sensor that uses a curved substrate to improve the image fidelity and reduce the dark current. At the same event, the Symposium on VLSI Technology, which takes place June 9-12 in Honolulu, engineers from TSMC will report on a CMOS image sensor with a 3D stacked architecture.

Sony's curved sensor is back side illuminated, with the curvature matched to the curved depth of field that comes from an integrated lens close to the surface of the chip. The use of a flexed substrate doubles the light sensitivity at the edge of the image and increases it at the centre by a factor of 1.4, according to the abstract of the paper. This provides options to relax the lens design in terms of F number. At the same time, the tensile stress of curving the substrate widens the energy band gap and thereby lowers the dark current.

TSMC's paper reports on replacing the conventional BSI carrier wafer with an ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. The engineers are due to report that, with appropriate layout design and process control, the impact of through-silicon-vias (TSVs) on the 1.1µm BSI CMOS image sensor's performance can be minimised.

The abstract to paper 21.3 states that the stacked sensor exhibits comparable pixel performance to conventional BSI. It points out that this allows separate optimisation of the sensor processes and should lead to improvement of dark current performance.

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