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Protecting chips against electric floods

12 May 2014  | Dushyant Juneja

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Electrical current, made up of minute charged particles, naturally flows from the higher voltage to lower; like a river flowing from the mountains to the sea. The integrated circuit technology exploits upon this spontaneous flow like a dam, producing what seems like a wonder to the uninformed observer. Indeed, this flow plays as fundamental a role to the chip as river plays to the civilisation. The analogy, however, does not end here. Just like the city needs its own emergency arrangements to tackle with natural disasters like floods, the modern chip needs to guard itself against "electric floods."

"Electric floods," or more precisely, "charge floods," are a prominent concern to chip manufacturers today. Electric charge is fundamental in the nature around us: A mere rubbing of two suitable materials is enough to demonstrate these charges. A typical human body may become a storehouse of sufficient charge just by a casual stroll across the carpet. And since nature loves to restore its balance, one may experience a minor shock when touching the door knob or the metal cupboard thereafter. This is effectively due to the rapid flow of accumulated charge from the body back to the ground.

While the human body is unaffected by such minor shocks, these shocks may contain enough charge beyond a typical IC's capacity. When forced with such a rapid charge flow, the delicate chip can easily collapse. Such a collapse is called an Electro-static Discharge (ESD) failure, and is similar to the destruction a large rapid flood effects an unguarded city. In the worst case, it may lead the chip and the entire sub-system ineffective, causing significant losses. The concern rises in applications where the chip may be in proximity with high voltage devices, like industrial communications.

Chip manufacturers hence like to make their chip "flood proof" by classifying these failures and including several guard mechanisms. A typical chip may in fact contain as much as 10 per cent of its area dedicated to such guard mechanisms, typically called the ESD pad ring. To understand this protection mechanism, it is instructive to reflect back upon the analogy of a flood in the city.

A flood-prone but properly planned city, apart from the core residential and working areas, may also include a flood dam and flood gates to divert the undesired water away. While they would be shut off during normal operation of the city, they would prove vital in case of emergent floods. For a chip or a board, these flood gates are designed to open automatically as soon as an undesirable quantity of electric charge is perceived to be coming into the core. A typical mechanism for such protection would be to divert the entire charge to a central pool, from where it can find its way out through some other pin.

ESD pad ring
The mechanism is incorporated using the ESD Pad ring. This additional circuitry consists of several protection circuits. For instance, all IO pins are equipped with diode based "valves" for diverting any excess charge on pins to supplies. The supplies are further equipped with ESD clamps to protect internal circuitry from over voltages. These clamps help connect to the pad ring core as well, and operate during abnormal conditions. Since all pins will connect to some supply in a circuit, the pad ring will also have a connection to every other pin. An exhaustive net is hence activated during an ESD event that can connect every required pin to other pins to drain away the excess charge. The chip, overall, acts as if short-circuited or bypassed by the pad ring.

However, care must be taken that a normal flow is not calculated as an overflow, and that the automatic security can well differentiate the two. Since all of this must be done irrespective of whether the chip is activated or not, the design difficulty takes an entirely new level. Figures 1-3 demonstrate the concept more graphically.

Figure 1: Unguarded chip under normal operation, limited current capacity.

Figure 2: Unguarded Chip under ESD Zapping, destroyed by excess charge.

Figure 3: Guarded Chip under ESD zapping. Additional ESD devices drain out the excess charge flow.

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