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Boundary scan: Benefits and challenges

26 May 2014  | Chintan Panchal, Parth Rao

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Additional Pins: The second most apparent penalty is the need to add dedicated test pins to the chip. IEEE Std. 1149.1 calls for a minimum of four pins. While the fifth test logic reset (TRST*) pin is optional, feedback from some IC manufacturers indicates that they may also provide this pin. The TAP can access many testability features within a design that might otherwise require package pins for additional data or control access. The four or five pins required by the TAP may therefore frequently provide for all test purposes. Viewed in this way, the requirement for a number pins dedicated to test is not unusual—many ICs today use several dedicated test pins to allow them to be tested economically.

Higher Design Effort: Since there is additional circuitry associated with boundary scan, it can be safely assumed that some form of additional design effort will be required. Application-specific ICs (ASICs) are being developed that have the boundary scan path built into the periphery of the base logic array.

Performance Degradation: Performance is another consideration. The multiplexer that feeds the system pin could add two gate delays. Combined with the additional delay due to the input loading, the propagation delay of signals leaving the chip would increase. Similarly, the delays experienced by signals entering the chip would increase if boundary scan cells that include multiplexers in the pin-to-logic data path are used. The importance of these additional delays clearly depends on the application for which the chip is intended.

It must be pointed out that the use of multiplexers at output pins to permit observation of test data from the core of the design is already commonplace. Many ASIC companies require that complex macro-cells are connected in this way to ensure that test stimuli can be applied. After considering this situation, we can say that there is no additional delay introduced by the inclusion of a boundary scan path. The multiplexer at the output needs to be widened to allow for the input from the boundary scan shift-register stage.

Power Consumption: As circuits are added to the basic design, an increase in the power consumption of the component is expected. For CMOS IC designs, the increase in consumption during normal operation will be small because the boundary scan path and much of the other test logic will be inactive. Only the TAP controller will remain active since, in the absence of a TRST* input, it must continue to be clocked with the test mode select (TMS) input. TMS should be driven to logic 1 to ensure that the controller can return to the Test—Logic—Reset state following any upset.

Implementation considerations
There are list of design rules which describe the limitations of an In-Circuit Test system (ICT) compared to JTAG test system.

ICT design rules
 • 0.00196 square inch per test point
 • 1,000 test points means 2 square inches lost area on the PCB
 • Provide keep-aways (protected area) around test points for tall components
 • Keep test points away from board edge
 • Avoid probing both sides of the board
 • Avoid moving test points after the fixture has been constructed

Additional Benefits of JTAG over ICT: Boundary scan saves space:
 • Save 2 square inches for every 1,000 test points eliminated
 • Traces no longer needed to the test points

The additional benefits of JTAG over the ICT will be considered as a trade off between the area overhead due to additional circuitry, and test points elimination.

In short, the boundary scan technique has both positive and negative impacts at the board and system level test. Boundary scan is economical as it speeds up the test process, ensuring higher yields from manufacturing and many other cost-saving measures. It can generate additional solutions for the EMS by expanding into new areas like functional test. Alongside of all these advantages, boundary scan has two major drawbacks: area overhead, and additional design effort. After comparing the ICT system requirements of test points and fixtures, boundary scan still manages to balance its area overhead and design efforts.

Today, with increasing die sizes and shrinking technology nodes, JTAG has manifold benefits over ICT testing. This advantage increases with the increasing complexity and size of the IC. We have realised significant gains with designs of over 30 million gates and 10 million scan cells at 28nm technology using JTAG.

About the author
Chintan Panchal works with eInfochips ASIC division.

Rao Parth is an ASIC DFT engineer.

To download the PDF version of this article, click here.

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