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Evaluating the approaches to hierarchical analysis

18 Jun 2014  | Ruben Molina

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Precise application of constraints for nets and paths that cross a block boundary also pose a challenge. For example, the user might wish to propagate constants through sequential elements. In this case, the constant propagation cannot be performed by simply asserting constants at block boundaries and then propagating them through the block. If multiple iterations of block analysis are required, the convergence is difficult to determine. In general, if the user's constraints refer to the flat design context, the hierarchical approach must create block-level constraints from them, and then attempt to manage the block-level constraints transparently. Any incremental addition/updating of user constraints must be reconciled with the block-level constraint.

Focus on scope-based analysis
When one looks at signoff timing analysis it is inferred that the results must be signoff accurate. It is the reason there is a whole market segment of tools dedicated to signoff timing. With this in mind, full flat analysis is the standard for handling all physical and electrical context based impacts on timing analysis. Cadence has already introduced full flat distributed timing analysis in the Tempus Timing Signoff Solution to dramatically improve runtime and capacity. There is almost no limit to the design sizes that can now be analysed flat. However, it is common for subsets of the design to go through final iterations just before tape-out. For these situations today, a full chip analysis is required in order to properly take into account the in context effects or a compromised solution such as ETM or ILM approach can be used to save on the runtime of the entire design.

Einstein once said, ""Everything should be made as simple as possible, but not simpler." Applying this principle to the analysis of a block of a design means ultimately to time that portion flat because it is the most straight forward (i.e., "simple") and accurate solution. Making the solution too simple results in compromised solutions we have already discussed. So the question remains how to only time that portion of the design that is influenced by the changed block. The answer is "scope based analysis.

Cadence has developed, within Tempus, the ability to dynamically abstract only those portions of the design that a user wants to analyse, and do it with full chip level context. In this approach, users define the change space at the level of granularity equal to physical/logical block boundaries. Once the blocks or top level scope is provided to Tempus, dynamic abstraction of the design is done under the hood. The resulting carved out design is then analysed which results in significant runtime and memory footprint reduction. Figure 5 shows pictorially that scope based analysis can be run for blocks or the top level if that is the only portion of the design that was changed.

Figure 5: Scope based analysis.

Some of the key benefits to the approach are as follows:

 • Scope based analysis allows the tool to operate with the same user timing scripts and constraints that are used for flat timing analysis, without any significant modification. In addition, the interactive nature of the timing tool, for applying constraints, ECOs and querying must be preserved. In other words, there is no change to the use model of timing analysis.
 • All reporting commands operate and produce the same results with scope based analysis, as with flat timing analysis. This is especially important because any deviation in the results, or the way the results are presented, would cause the user to spend needless time in correlation and debug.
 • Significant speed up in runtime over full flat analysis. Typically analysis is performed 2-3 times faster and consumes significantly less peak memory than a full flat approach. In addition, each scope based analysis can be run in parallel by leveraging Tempus distributed processing, if required.
 • Full compatibility with MMMC analysis. The user-script set-up for defining constraints and analysis views is honoured as-is.

The timing closure and signoff solutions in use today have been extended to include advanced, more complex functionality to address SI and MMMC analysis and variation. Though these solutions extend capacity and reduce runtime they are all compromised solutions for final signoff. Ultimately, the heart of a full timing signoff solution is still rooted in its ability to accurately take into account full chip level design context. The only way to achieve this without compromising accuracy or physical design methodology is with full flat level timing analysis.

Cadence has introduced the next generation of timing analysis tools in the Tempus Timing Signoff Solution, with the ability to run hundreds of millions of cells flat, or intelligently run only a portion of the design at a fraction of the time. Tempus both extends capacity and addresses runtime by scaling the use of distributed processing power with design size. Taking this one step further, the Tempus now introduces the concept of scope based analysis to accurately and efficiently analyse portions of the design that have changed or are affected by the design change. At the root of the solution is intelligent abstraction of the affected design space which is ultimately run in a true flat level analysis. This solution comes without many of the compromises that are seen by utilising ETMs or ILMs to maximise runtime and capacity. Nor does scope based analysis require the iterative analysis and constraint refinement seen in existing alternative flows.

About the author
Ruben Molina contributed this article.

To download the PDF version of this article, click here.

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