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Address challenges for high-speed ADCs, radar systems

24 Jun 2014  | Duncan Bosworth

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Radar waveform bandwidths can vary dramatically depending on the application, for example some Synthetic Aperture Imaging Radar Waveforms requires hundreds of MHz while tracking radars may use waveforms that are tens of MHz wide or even less. In the past, moving a GSPS ADC closer to the antenna would have meant that in some instances vast amounts of unwanted bandwidth were transported to the FPGA or processor.

In modern FPGAs and high-speed ADCs a significant proportion, if not the majority of the power consumption, is related to the power dissipated in the interfaces to the device, thus transferring significant amounts of unwanted bandwidth needlessly increases the power of the system. In future multi-mode radars the ability to dynamically enable a DDC provides a significant advantage, offloading complex processing otherwise located in the FPGA.

The DDC combines a digital numerically controlled oscillator (NCO) and decimating filters, providing the ability to select the signal bandwidth and signal location from within the high-speed ADC's Nyquist band and transfer only the appropriate data needed to the signal processing devices. For example, consider radar using a 30MHz bandwidth waveform at an IF of 800MHz. If this is sampled using an A/D converter at a sample rate of 2.0 GSPS to a resolution of 12 bits, the output bandwidth of the data would be 1000MHz, far in excess of the signal bandwidth, and the output data rate from the converter would be 3.0 GB/s.

If the data is decimated by a factor of 16 using a DDC, not only does the decimation provide some increased noise reduction but the output data rate is reduced to below 625 MB/s, which enables data transportation using only a single JESD204B lane! This significantly reduces the overall system power required. With the ability to dynamically configure the DDCs or bypass them as needed, new high-speed ADCs provide the option of switching between different modes to support power and implement optimised solutions as needed and enable the feature sets needed for cognitive radar applications.

New GSPS A/D converters are providing significant options to the radar system architect, with analogue bandwidths and sample rates that enable component count reduction or direct RF sampling. With JESD204B interfaces and embedded DSP options, there is no longer a need to trade power and board complexity for these benefits. The ability to dynamically configure the high-speed ADC provides multi-function support and meets the goal of creating an all-digital cognitive radar system.

About the author
Duncan Bosworth is with Analog Devices.

To download the PDF version of this article, click here.

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