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Assessing production outlier removal techniques

25 Jun 2014  | Wesley Smith

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Makers of automotive and medical ICs widely employ Part Average Testing (PAT), an adaptive test technique for improving the quality and reliability of devices used in air bag sensors, engine controls, pacemakers and other high reliability applications. Documented by the Automotive Electronics Council in the AEC-Q001 guidelines, PAT is based on the premise that "outliers are evil". That is, parts that have atypical characteristics tend to be higher contributors to infant mortality and long-term reliability problems- even when they pass all data sheet specs. Industry studies have shown that implementing PAT can reduce DPM (defects per million) rates by as much as 30% to 60%.

Smartphone and tablet manufacturers have begun to mandate the use of PAT by their semiconductor suppliers, and test operations groups are starting to deploy the process at their wafer sort and/or final test facilities. PAT and other outlier removal techniques, however, always involve some trade-off between incremental yield loss and incremental quality improvement. At smartphone IC volumes, a fraction of a per cent of additional yield loss or field returns can represent many millions of devices, which can have a dramatic effect on cost and/or brand reputation. As a result, IC manufacturers are looking for more sophisticated algorithms that judge outliers based on more stringent criteria than just 6-sigma limits on a Gaussian distribution. I'll describe a number of outlier removal techniques in use today that are helping high volume device manufacturers meet the stringent quality standards imposed by automotive and mobile markets, while keeping unnecessary yield loss to a bare minimum.


Avoid excessive yield loss
Yield is a terrible thing to waste, but inevitably a significant number of perfectly good parts are scrapped along with the real outliers that could one day cause your car to stall or your phone to crash (or vice-versa). A classic cause of unnecessary yield loss is the use of test limits that are too rigid and based on an idealized Gaussian distribution. In practice, parametric tests often have non-Gaussian distributions such as Log Normal, Multi-modal or Gaussian with a tail, and trying to impose classic ±6 σ limits may result in rejecting too many good parts while missing some real outliers. Figure 1 shows such a case where the natural distribution is Log Normal, which would call for asymmetric limits of +9 σ/-3 σ, whereas normal 6 σ limits would incorrectly indict outliers in the long tail. The moral of the story is that PAT software must be smart enough to recognise the nature of the distribution for each test and set the limits accordingly.


Figure 1: Example of Log Normal distribution for a test, which would result in false outliers if standard PAT limits were used.


Another common cause of unnecessary PAT yield loss is site-site variation on the ATE (Automatic Test Equipment), which may create measurement offsets that result in some parts exceeding the computed PAT limits. To avoid this, the dynamic PAT limits must also take into account the site-specific offsets.
Catch hidden outliers
Even more insidious than throwing away good parts is letting real outliers slip through the test process. While dynamic PAT at wafer sort has the benefit of seeing all the test results before it calculates the PAT limits, it can still miss some outliers that are hiding in the normal variability of die across the wafer. Parametric variations in different areas of the wafer are normal; for example, the die near the centre of the wafer may have parametric results that are somewhat different than those on the edge. Because all die on a wafer are fabricated at the same time on the same equipment, however, a die in one area of the wafer with a test result significantly different than its most immediate neighbours is most likely defective, and should be binned out.

Fortunately, there are some sophisticated algorithms that can help identify the outliers that simple rules might miss. One such algorithm for wafer sort is called NNR (Nearest Neighbour Residual). Using NNR, the PAT limits for each die are determined based on the distribution of test values of the die surrounding it. This shrinks the context for each test to a small region of the wafer so that a local outlier would stand out.

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