Path: EDN Asia >> News Centre >> Computing/Peripherals >> Intel bares enhanced massive parallel processor
Computing/Peripherals Share print

Intel bares enhanced massive parallel processor

24 Jun 2014  | R. Colin Johnson

Share this page with your friends

At the International Supercomputer Conference in Germany, Intel disclosed the details of Xeon Phi, its massively parallel processor, as well as a new interconnection fabric based on the company's silicon photonics advances, and an educational programme designed to allow new programmers to learn how to code for parallel processors.

"In just 16 years, we've seen the fastest supercomputer in the world at 3TFLOPS migrate down to a single socket," Charles Wuischpard, VP and general manager of Intel Workstations and High Performance Computing Data Centre Group told EE Times in a conference call.

Intel has been talking about a new version of its massively parallel Xeon Phi processor—currently with 60 cores per chip—but at ISC-14 unveiled many more, but not all, of the details about the new chips, which will be available in the second half of 2015. Its current-generation Xeon Phi is a 1TFLOP chip cast in 22nm CMOS and sold on a PCIe board in several versions. The Green500 list pronounced it the most power-efficient parallel processor in the world. The Top500 supercomputer list just announced the Xeon Phi powered Tianhe-2 (Milky Way 2) supercomputer at the National Supercomputing Centre in Guangzhou, China, as the fastest in the world for the third time running.

"We have a new Xeon Phi processor coming in the future called Knights Landing," said Wuischpard. "The first thing to note is that it will be 3TFLOPS in a single package, which will be available in the second half of 2015, with at least as many processors, but based on the Silvermount architecture and connected by a low-latency mesh."

HPC growth rate

Figure 1: Intel predicts that high-performance computers will grow at a rate of 20 per cent per year as prices drop, inducing more segments to purchase them. (Source: Intel)

The previous MIC processor—called Knights Corner—was based on a special microarchitecture created just for it, but the new-generation Knights Landing Xeon Phi will be based on Silvermont modified for Intel's 14nm process. The Silvermont architecture has also been heavily modified to add key features, such as an AVX512 vector processor and four threads per core, versus the current Silvermont, which has no AVX512 support and just one thread per core.

1 • 2 Next Page Last Page

Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.

Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming

News | Products | Design Features | Regional Roundup | Tech Impact