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3bit, 32-layer V-NAND chips to boost SSDs

06 Aug 2014  | Rick Merritt

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"We decided over the last couple months to open this up to the industry," Brennan told EE Times.

"We took a risk putting this out before we have all the questions answered, but we don't think it's right to invite collaboration when you have a fully baked solution," he said.

Making data about the performance of flash chips available to storage applications is a first step. The initiative ultimately aims to open up flash controllers as a distributed resource for any tasks in a datacenter, he said.

"There will be hundreds if not thousands of SSDs in the datacenter over time with their processors only busy at peak times," he told attendee.

The initial work took place in Samsung labs in Korea and San Jose using an SSD with a serial ATA interface. Samsung has not decided yet whether it will turn its lab work into a product, Brennan told EE Times.

The news came just minutes after a datacenter manager from China's Alibaba called for closer data links between flash memory chips and applications using them. "This is the sort of applications-centric approach we have been seeking," Wu Peng, the Alibaba keynoter, told EE Times after the Samsung talk.

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Samsung got more consistent I/O operations/second linking flash and apps data via its controller on a SATA SSD (above) and got low latency with fewer IOPS when intelligently checking with apps about when to do garbage collection (below).

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