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Built-in self-test schemes for ADCs

09 Sep 2014  | Kushal Kamal, Vandana Sapra

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With the growing number of complex circuits being integrated into SoCs, their testing requirements have become equally complex. While there are well established test strategies for digital circuits, the testing of analogue circuits is quite expensive and challenging. A commonly encountered analogue circuit is the analogue to digital converter (ADC), and in this paper we will discuss the conventional method of testing ADCs, as well as the various built-in self-test schemes that can be used for their testing.

The traditional method of testing employs Automatic Test Equipment (ATE) feeding in arbitrary waveforms or test patterns to Device-Under-Test (DUT) and collecting test responses as seen in figure 1. One popular and simplistic method to test an ADC is by a simple Ramp Test in which the ADC is configured to perform back to back conversions on a single channel. Then, a suitable ramp voltage is applied to the same channel so that all possible digital codes appear at the ADC output a fixed number of times. This output code is then compared against the expected ADC output. The difference between the expected and the actual output is calculated. The max. to min. variation of this difference is called TUE, or Total Unadjusted Error. On the test equipment, we program it to fail the part if the TUE is beyond an acceptable number. In Automotive MCUs, this figure can be up to ±2LSbs. Hence, if the ADC has a TUE of more than ±2LSbs, it is considered a bad part.

Figure 1: Conventional test architecture.

The importance of ramp rate is evident from the above description. Let us see how an optimum ramp rate can be calculated, with the help of an example. Let us consider a 12 bit ADC that works at the rate of 1Mega Samples Per Second (MSPS) for a Full-Scale range of 0-5V. The ADC gives 000(Hex) for input voltage of 0V and FFF (Hex) for 5V. The ADC output varies from 000 to FFF in 4096 steps as voltage rises from 0V to 5V. That means ADC output code changes by 1 when Input voltage increases by (5V-0V)/4096, that is, 1.22mV. If it is desired to get an output digital code to appear six times, we need to make sure that the ADC input does not increase by more than 1.22mV while ADC has made six conversions. With this understanding, the desired ramp rate can be calculated. The ADC gives one output code in 1µs. The input voltage must not change by more than 1.22mV in 6µs. Thus the desired ramp rate is 1.22mV/6µs or 0.203mV/µs.

There are multiple inherent disadvantages associated with this method:

 • A lot of Input and output data has to be stored and transferred from and to DUT.
 • Effects of parasitic capacitances and external noise need to be taken into account.
 • Measurement and evaluation of test responses takes considerable time, which directly adds onto production cost.
 • For diagnostics and debug purposes, extra pins are required for tester that severely debilitates the parallel testing of different circuits.
A better option is to integrate self test hardware onto the chip. Systems equipped with self test hardware are capable of autonomous testing with no external stimulus generation and measurement requirement.

Built-in self test (BIST) schemes can also be categorised into offline and online. Offline BIST interrupts the normal operation and is not suited for real time environment, whereas online BIST runs in the background with no impact on normal operation. Online BIST requires redundant modules, so to implement this you would incur some cost. Online BIST can be further classified into concurrent and non-concurrent testing. In concurrent testing, normal functioning and testing can be done simultaneously, whereas in non-concurrent, testing is done in idle periods of the system.

The most simplified BIST test technique requires an on-chip waveform generator which generates an analogue signal of higher resolution than the ADC, and records the number of times each unique digital code appears at the output. When choosing between various on chip waveform generators, it has been found that using a triangular wave as input rather than a sinusoidal input has been advantageous. It saves memory required to save the output data [1] and makes the calculations easy which in turn also saves the hardware operating resources. A histogram is created with the available data. The actual histogram is compared with that of an ideal one and various calculations are performed on the recorded data to compute Offset error, Gain error, Differential and Integral Non-Linearity error. A missing code is identified if corresponding count for any code is zero. For ramp input stimulus, the offset error is given by difference between the two extreme code histograms. Gain error is computed by comparing a number of non extreme codes' histogram with their ideal values. DNL error is represented by the relative difference in actual and ideal ADC for each step size. INL is calculated by accumulating the sum of the DNL of all preceding codes.

Figure 2: Histograms illustrating slight clipping in the ADC channel.

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