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RDIMM vs LRDIMM: What changed for the better?

10 Sep 2014  | Douglas Malech

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The need for higher speed and memory capacity has never been more intense as big data business analytics, real-time data for social media, and mobile applications continue their growth trajectory. Over the last few years, companies in the memory eco-system have worked closely to continue advancing the system memory roadmap for enterprise applications. This article aims to highlight the advances the industry has made with the latest memory technology DDR4 and more specifically on DDR4 LRDIMM.

DDR4 LRDIMM (load reduced memory module) technology uses a distributed data buffer approach to accomplish memory bandwidth efficiencies when scaling to higher capacities and speed on the upcoming DDR4 enterprise server systems. This is in contrast to the unbuffered data approach used with DDR4 RDIMM (registered memory modules).

In figure 1, Gen1 DDR3 enterprise systems, such as E5-2600, had sub-optimal LRDIMM speed for all capacities due to reasons that will be described below. E5-2600 v2 made significant progress in improving LRDIMM value to end-users and reversed the speed inversion issue that existed on E5-2600. DDR4 LRDIMM is expected to launch memory sub-system performance to a new paradigm. DDR4 LRDIMM not only appeals to the highest capacities, but also to a much wider range of applications that require highest bandwidth and highest capacities.


Figure 1: LRDIMM vs. RDIMM speed improvement.


The eco-system has collectively made huge strides in ensuring that increases in LRDIMM speed translates into a corresponding scaling of LRDIMM memory bandwidth in GigaByte/second (GB/s). Speed is analogous to which track star can sprint the fastest for short periods of time; memory bandwidth is analogous to who crosses the finish line first.

To summarise the DDR4 improvements made by various stake-holders in the eco-system to improve the usable bandwidth in GB/s:

 • Improved LRDIMM architecture for better signal integrity on the data signals
 • Lower component latency through distributed data buffer components
 • Better intelligence and post-buffer awareness by the memory controller

How is it done?
To understand how DDR4 achieves this breakthrough in LRDIMM technology, stark contrasts can be shown with DDR3. DDR4 and DDR3 LRDIMMs both reduce the number of data loads to improve signal integrity on the memory module's data bus from a maximum of 4 data loads down to 1 data load. However, DDR4 introduces some additional features to reduce overall latency and improve signal integrity, leading to speeds comparable to DDR4 RDIMM. This equates to DDR4 LRDIMM meeting or exceeding DDR4 RDIMM bandwidth at all speeds and memory capacities.



LRDIMM Design: Centralized vs Distributed Buffers
A DDR3 LRDIMM has a memory buffer located in the centre of the module, as shown in figure 2. Similar to an RDIMM, the memory buffer (MB3518) buffers and retransmits the command, address, and clock signals to the DRAMs. In addition, the LRDIMM also buffers the DRAM I/O data bus. By buffering the I/O data, up to four DRAMs loads on the backside bus are reduced to one load on the frontside bus.


Figure 2: LRDIMM Design topology.


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