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DesignWare MIPI D-PHY reduces area, power by 50 per cent

18 Sep 2014

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Synopsys Inc. has cut the area and power consumption of its DesignWare MIPI D-PHY by 50 per cent compared to competitive solutions while increasing performance to 2.5Gbit/s per lane, reducing system-on-chip (SoC) silicon cost and extending battery life for mobile, consumer, and automotive applications.

Compliant to the MIPI D-PHY v1.2 specification and part of a complete solution with DesignWare MIPI DSI and CSI-2 Controllers and verification IP (VIP), the D-PHY reduces integration risk and the effort of connecting to a variety of image sensors and displays.

"Over the last 10 years, Synopsys has played an active role in MIPI Alliance working groups, contributing to the development and proliferation of MIPI Alliance technology," said Joel Huloux, chairman of the board of MIPI Alliance. "With the introduction of the latest DesignWare MIPI D-PHY, Synopsys helps designers take advantage of the high-performance and low-power capabilities specified in the D-PHY v1.2 specification to quickly deploy SoCs for high-end mobile, consumer, and automotive image sensor and display applications."

The DesignWare MIPI D-PHY is the physical layer used for MIPI CSI-2 and DSI Host and Device applications to connect image sensors and displays to SoCs in mobile and embedded applications. The DesignWare MIPI D-PHY is the first D-PHY that is compliant to the MIPI Alliance D-PHY v1.2 specification. For high-resolution output, four lanes of the DesignWare MIPI D-PHY can be aggregated to support 10Gbit/s speeds and eight data lanes can be aggregated to achieve 20Gbit/s speeds.

In addition, the DesignWare MIPI D-PHY's configurability options enable designers to reduce the number of SoC designs required to target multiple applications, minimising time-to-market.

"By delivering an extremely small-area and low-power D-PHY to the fast-paced and competitive mobile market, Synopsys helps designers differentiate their SoCs in both silicon cost and battery life," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "With a broad portfolio of high-quality IP supporting the latest MIPI Alliance standards, Synopsys enables designers to integrate the latest functionality into SoCs for the mobile and consumer markets."

The DesignWare MIPI D-PHY is available now in 16nm FinFET processes, with availability in 28nm processes scheduled for early 2015. VIP for MIPI D-PHY v1.2 is available now.

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