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Verification IP speeds up adoption of MIPI's PHY layer

19 Sep 2014

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Synopsys Inc. has unveiled a verification IP (VIP) for the MIPI Alliance MIPI C-PHY specification that uses three-phase digital coding techniques to provide higher performance for camera, display and SoC interfaces without affecting bandwidth. According to the company, the release of this VIP helps enable engineers to verify interfaces such as MIPI CSI-2 v1.3, which includes the MIPI C-PHY.

Synopsys, a contributing member of the MIPI Alliance, provides VIP and design IP that accelerate the adoption of MIPI-based standards in mobile and mobile-influenced industries, including automotive and medical, that can leverage MIPI Alliance standards such as those for display, camera and sensor interfaces. Synopsys VIP supports the MIPI Alliance protocol specifications including D-PHY, C-PHY and M-PHY and is based on a native SystemVerilog architecture for enhanced ease of use, performance and debug, enabling compliance checking of IP blocks and SoC interfaces.

Synopsys VIP, based on its next-generation architecture and implemented in native SystemVerilog, offers native performance, native debug with its Verdi tool, enhanced ease of use, configurability, coverage and source code compliance test suites, detailed the company. These capabilities substantially increase user productivity for one of the most difficult and time-consuming aspects of SoC design and verification. The Synopsys VIP library includes a broad portfolio of interface, bus and memory protocols.

The Synopsys VIP for M-PHY, D-PHY and C-PHY are available. C-PHY is included with the Synopsys VIP for CSI-2 v1.3.

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