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Boost performance with embedded Flash

08 Oct 2014  | Jae Song

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Mobile phones and tablets have become natural parts of the lives of their users worldwide. Considered an essential companion by many, these gadgets continue to push performance limits as they integrate enhanced nonvolatile memory and ever smarter power management. Thanks to a new embedded Flash (eFlash) process, fabless chip designers can now economically integrate better performing nonvolatile memory into mobile chips while conserving power. The new process is especially well suited for embedding flash into touch screen controllers (TSCs) and microcontroller units (MCUs).

The graphs that follow detail the key specifications for the new eFlash process at the 0.13 micron node. Fabless chip designers who seek to embed nonvolatile memory would be wise to consider these parameters before releasing their designs to a foundry.

Minimising disturbance
In this chart, the W/L disturbance is plotted under erase status according to stress time. There is no VT shift after long stress time compared to the maximum immunity time, 2.52ms.

Figure 1a: Word Line (W/L) Disturbance Free, Maximum immunity time 2.52ms.

Figure 1b: Bit Line (B/L) Disturbance, showing enough margin up to 200k program/erase cycles. The Bit Line disturbance shown is plotted under erase status according to the cycling accumulated times. There is a little VT shift after accumulated cycling but VT distribution shows enough margin.

Figure 1c: Sub Disturbance is plotted under program status – according to cycling accumulated times, showing no VT shift.

Enhancing data retention

Table: Data Retention (@100K P/E cycles) Results: Target >10 years @85°C with 100k P/E cycle was satisfied.

Figure 2: TTF Plot for DRB after 100k P/E cycles shows Time-To-Failure plot for Data Retention Bake after 100K Program/Erase cycles.

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