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Can cognitive layering meet challenges of power design?

03 Oct 2014  | Nick Flaherty

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He points to three key trends. Firstly, designers will do cognitive layering, even in these low-cost chips, with only just enough processing at the low level. Secondly, power and clock gating of everything to reduce the switching, reducing the amount of time power is applied to the device. Then, there are the architectural opportunities: instruction set optimisation to reduce the number of cycles, reducing the energy of the interconnect between the blocks with special purpose paths between the high activity areas and memory partitioning by powering on only enough memory for the application. This system architectural dimension is critically important, he says.

He points to inertial navigation as one of the classic problems for IoT. While low-cost accelerometer and gyroscope chips do a quite good job of knowing exactly where you are, there are some key challenges. You have six noisy sensors all feeding data, sampling 100 to 1,000sample/s and you need to use the redundant information to filter out the noise using Kalman filtering but this needs high accuracy and high levels of computation.

Using a configurable processor took a processor load of approximately 1m cycles per sample down to approximately 1,600 cycles per sample, so the power was driven down to the level of 10s ofµW to do this high data rate operation. This is the kind of sensor DSP application that is at the heart of the cognitive layering approach.

The other key factor is in modelling the system more accurately. Cadence has synthesised the Tensilica core and characterised it not at standard cell but using SPICE directly, extracting all the transistors and wires. This gives a more accurate power curve that is getting close to 1µW/MHz because we are not limited by the range of the characterisation and can operate at 0.8V +-10 per cent and still be comfortable above the threshold voltage, even when building in sufficient margin of manufacturing variability.

All of this leads to a split between the big, general purpose SoCs pushing the performance and process curve, and the more specialised IoT devices optimised for low cost, low power and very specific functions.

"I think design starts are going to respond to this explosive opportunity" he told EE Times. "SoC design starts will accelerate for new cognitive layering designs that aren't all bleeding edge and it will drive partitioning more and more between 'often on' and 'rarely on.' These will have a design cycle of a few months and a team of maybe dozen people so you can do it for a million dollars—that's the kind of design automation that's possible without giving up flexibility and we are working that out in the different areas right now."

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