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Verification IP for M-PCIe speeds up debug, coverage closure

09 Oct 2014

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Synopsys Inc. has released its verification IP (VIP) for the M-PCIe protocol, including built-in M-PHY as defined by the MIPI Alliance specification. Based on its native SystemVerilog VIP architecture, the VIP for M-PCIe technology claims to deliver enhanced performance, ease of use and debug in SystemVerilog UVM environments.

The Synopsys VIP for M-PCIe is integrated with Synopsys' Verdi protocol analyser, a protocol-aware environment that speeds debug by providing simplified views of protocol traffic. The addition of M-PCIe technology to Synopsys' VIP for PCI Express architecture provides mobile and low power PCI Express design and integration teams with a full-featured, SystemVerilog UVM solution to accelerate verification and coverage closure, noted Synopsys.

Synopsys' complete M-PCIe IP solution consisting of verification IP, a silicon-proven DesignWare M-PCIe digital controller and M-PHY enables project teams to accelerate development of M-PCIe-based SoCs and hit critical market windows, the company added.

Synopsys' verification IP for M-PCIe is available for early adopters as a stand-alone title and as part of Synopsys' Verification IP Library as well as Verification Compiler. The DesignWare M-PCIe digital controller and PHY are also available.

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