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Addressing cost issues in low pin count test designs

23 Oct 2014  | Pradeep Nagaraj

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To ease concerns about longer test times due to the shift operation of the deserializer/serializer registers, there are two possible options. In the aforementioned example, if the tester can supply a clock that is up to 8x faster than scan frequency, then the overhead due to the deserializer shift is nullified and the total test time is further reduced with no scan clock timing impact. The other option is to increase the scan bandwidth available – for instance, going from 1SI, 1SO pair to 2SI, 2SO reduces test time by 2x.

Figure 4: Results from an automotive design.

Other approaches for LPCT
There are solutions developed by DFT designers to address LPCT needs for their designs. For non-compressed smaller designs, one methodology is to make use of a single scan data pin both to load the stimulus and unload the response by encoding the scan data. The advantage of this approach is that the number of pins that can be used for test can be as low as two (including the scan clock). The disadvantages, though, are that the test times would be doubled, the complexity of DFT hardware due to encoding/decoding schemes would increase, and the solution is restricted to fairly small digital designs (1k-10k flip-flops).

Sequential-based test compression using either a pseudo-random pattern generator (PRPG) on the input side and/or a MISR on the output side provides an alternative opportunity to achieve low pin count compression.

We have discussed a number of possible ways to address LPCT challenges. The deserializer/serializer-based compression approach provides the ability to target high-quality ATPG patterns via a single scan-input scan-output interface. This approach has been proven on silicon with numerous automotive, MCU, and embedded processor designs ranging from 100k to multi-million flip-flops.

About the author
Pradeep Nagaraj

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