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Cadence rolls multi-protocol DDR4 and LPDDR4 IP sol'ns

17 Oct 2014

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Cadence Design Systems Inc. has unleashed what it describes as the industry's first multi-protocol DDR4 and LPDDR4 intellectual property (IP) solution. According to the company, the Cadence DDR controller and PHY IP can scale up to 3200Mb/s, enabling designers to leverage higher performance DDR4 and LPDDR4 DRAMs when they become available, without the need to redesign their SoCs.

With a single, multi-protocol IP, designers can easily address changing memory and system cost requirements in consumer, mobile and enterprise applications. They can select the optimal DRAM subsystem implementation for their specific application after the SoC has already been designed.

DDR4 is primarily used in enterprise applications requiring high-capacity and high-reliability DRAM subsystems. LPDDR4 meets the power/performance requirements of mobile applications.

Consumer applications, on the other hand, have traditionally used DDR3 DRAMs, moving to DDR4 to benefit from DRAM commodity pricing. Over time, performance requirements for these application areas are expected to grow, while performance levels for LPDDR4 are seen to improve. With the latest IP, designers can easily migrate from DDR4 to LPDDR4 without a chip redesign, the company noted.

The Cadence multi-protocol DDR IP solution is available for early adopters, with general availability scheduled for 4Q14.

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