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ASSET InterTech, Mentor products boast IJTAG interoperability

24 Oct 2014

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ASSET InterTech and Mentor InterTech have announced IJTAG interoperability on their products for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard. The companies said the feature allows them to accurately debug and isolate issues in either a complex SoC or on the circuit board where the chip has been deployed.

IJTAG resources, including embedded instruments and a network connecting them, are inserted into a chip with Mentor's Tessent IJTAG solution. These instruments then allow engineers to verify and characterise the functionality and performance of the SoC at the chip level. When deployed on a circuit board, ASSET's ScanWorks tool will be able to provide a debug loop by accessing IJTAG resources to isolate problems in both the SoC and the circuit board. Issues found at the chip level can be corrected before additional devices are fabricated, the companies noted.

A series of IJTAG workshops is being planned by ASSET and Mentor for the spring of 2015. Attendance at one half-day session is priced at $295.




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