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Simulation characterisation sol'n eases mixed-signal designs

29 Oct 2014

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Cadence Design Systems Inc. has introduced a characterisation solution that the company touts as the industry's first dynamic simulation characterisation solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os. Built upon the Cadence Liberate characterisation platform, the Virtuoso Liberate AMS characterises post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20 times faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate SoC signoff.

With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros. To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analogue paths and modelling it into a final Liberty library.

To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterise large mixed-signal blocks. This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterises each partition with true SPICE accuracy to create highly accurate library models.

For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analogue Design Environment XL and leverages Virtuoso Analogue Design Environment XL test benches and setup to quickly move from circuit design validation into library generation.

The Virtuoso Liberate AMS is available.




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