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DCD releases instruction smart trace for 8051 architecture

10 Nov 2014  | Graham Prophet

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Digital Core Design (DCD) has improved its 8051 line-up with the addition of an instruction smart trace (IST). According to the company, beginning from the DP8051, through the DP80390, to the fastest 8051-architecture core, the DQ8051 can efficiently cut trace memory size and increase traced program history.

Instruction Smart Trace is an inherent part of the DoCD hardware debugger, which provides debugging capability for SoC designs. Unlike other on-chip debuggers, the tool provides non-intrusive debugging of a running application and saves designer's time, thanks to the hardware trace, called Instructions Smart Trace buffer (IST), stated DCD.

Instruction smart trace

The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn't capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method not only saves time, but also allows improving the size of the IST buffer and extending the trace history. "For example, by using 256 bytes of trace memory, we can store 128 program branches and decode much more program history, since the executed program is composed of normal opcodes (mov, add, mul, anl, etc.) and branches," explained Tomek Krzyzak, VCEO of DCD. "Based on this information stored in IST hardware memory, our DoCD.exe and Keil driver decode executed program and display this information as an ASM code and C code in trace history."

The DoCD Instruction Smart Trace buffer is configurable up to 8192 levels and is completely transparent for the debugged application. Its functionality enables real-time capture of executed instructions. Thanks to it, the engineer can later read-back to track down the history of executed code, by using the DoCD debug software. Instruction Smart Trace captures instructions in a smart and non-intrusive way, which means that it doesn't capture addresses of all executed instructions, but only instructions related to the start of the tracing, conditional jumps and interrupts.

As an example, the trace buffer is 2KB, which means that up to 1024 levels can be captured. It gives much greater history than 1024 instructions executed by the CPU. In the typical application IST enables execution of over 10k instructions, depending on how many conditional jumps and interrupts have been executed by the CPU.

IST has also configurable start/stop triggers, so the engineer can set the condition at which instruction tracing starts, but also when it should stop. The trace buffer can also be changed or disabled dynamically. The IST uses the end of SXDM memory space, allowing it to share the trace memory with the debugged programs. When the debugging is finished, it assigns the whole memory back to the application.

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