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HMC 2.0 controller IP takes on next-gen networks

20 Nov 2014

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Open-Silicon developed a comprehensive Hybrid Memory Cube (HMC) 2.0 controller solution as licensable Intellectual Property (IP) that will enable SoC designers to take immediate advantage of the performance gains afforded by the emerging memory standard.

Building upon its experience in working with customers to integrate earlier generations of this critical memory controller interface, Open-Silicon now offers HMC IP and the integration environment required to speed design, reduce cost and ensure product manufacturability. The company is already engaged with a lead customer to integrate the new HMC 2.0 controller IP into devices for applications such as high-speed networking equipment.

HMC is an innovation in DRAM memory architecture that sets a new standard for memory performance, power, reliability and cost. Governed by the Hybrid Memory Cube Consortium (HMCC), the specification fundamentally changes the way memory is built into a system by leveraging 3D packaging to connect multiple DRAM arrays to logic using through silicon vias (TSVs). The HMC 2.0 standard, recently ratified by the HMCC, specifies data rates up to 30Gbit/s.

"Our extensive background with both the integration of HMC IP and advanced design techniques is enabling a new generation of ASICs designed to address the growing bandwidth requirements of 100G and 400G networks, as well as high-performance computing," said Hans Bouwmeester, VP of IP and Engineering Operations at Open-Silicon. "As a developer member of the HMCC, we are actively involved in defining the specification, and can deliver standards-compliant IP as soon as the standard is ratified."

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