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Prototyping kits speed up software dev't, IP integration

21 Nov 2014

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Synopsys Inc. has extended its IP Accelerated initiative with DesignWare IP prototyping kits for 10 interface protocols that include USB 3.0, SSIC, PCI Express 2.0, PCI Express 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0 and JEDEC UFS. According to the company, the prototyping kits offer the necessary hardware and software elements needed to cut IP prototyping and integration effort by up to six weeks.

With the IP prototyping kits, hardware designers have a proven reference design that can be easily modified to explore design trade-offs and validate a specific configuration of the IP, and software developers have a proven target for early software bring-up, debug and test, noted Synopsys.

With the increase in SoC hardware and software complexity, companies need more from their IP providers to help meet their time-to-market schedules. To help address designers' growing SoC design and integration challenges, DesignWare IP prototyping kits provide proven reference designs that enable designers to start implementing the IP in an SoC context in minutes. The kits include a Synopsys HAPS-DX FPGA-based prototyping system with pre-configured IP and SoC integration logic, a PHY daughterboard, simulation testbench, reference drivers and application examples. The kits include either a host PC connection running the target operating system such as Windows, Linux or others, or a DesignWare ARC processor-based 32bit software development platform running Linux. Designers can modify the standard IP configuration for their target application through a fast iteration flow consisting of Synopsys' coreConsultant IP configuration tool, Synopsys' ProtoCompiler DX development and debug tool, and compilation scripts.

The DesignWare IP prototyping kits for USB 3.0, SSIC, PCI Express 2.0, PCI Express 3.0, DDR3, LPDDR3, LPDDR2, MIPI CSI-2, HDMI 2.0 and JEDEC UFS protocols are available.




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