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Zero-drift amps for precision design (Part 1)

16 Dec 2014  | Stephan Baier

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Self-correcting or 'zero-drift' operational amplifiers, as this device group is now commonly labelled, are getting ever closer to becoming the textbook ideal amplifier block. And they are now readily available in a variety of performance brackets, such as Low-Power or Wide Bandwidth. As Zero-Drift op amps promise to make their life easier (and rightfully so) it's no wonder they are getting increased attention from system designers of all industry segments While the heavy use of digital circuitry, in what used to be a simple three-stage, time-continuous analogue integrated circuit, may still cause scepticism with some designers with extensive analogue hardware design experience, the latest Zero-Drift amplifiers should help alleviate the scepticism.

Advances in CMOS technology and clever op-amp architectures have helped make the internal workings of this amplifier class mostly transparent to the hardware designer. This article reviews some of the latest advances in this group of 'digitally enhanced analogue' devices, and addresses some unique characteristics of Zero-Drift amplifiers. These characteristics, such as their noise spectrum and ultra-low drift, offer great performance opportunities. But they also need to be sufficiently understood, in order to maintain high levels of precision when incorporating them into the signal path.

Latest advances in zero-drift op amps
Compared to the textbook op amp, Zero-Drift amplifiers offer a number of highly desirable performance specifications. DC open-loop gain is typically very high, in excess of 140 dB. This is a result of the 3-stage amplifier topology, as will be discussed later in this article. Secondly, the internal self-correction reduces the initial offset voltage down to extremely small levels; usually down into the single micro-volt range. In order to obtain such low offset on standard-precision (time-continuous) op amps, vendors had to resort to either chip-level laser trimming or some form of package-level trim. Both options require on-chip circuitry and, more importantly, add to the test time and, therefore, cost. While the design of Zero-Drift amplifiers also necessitates additional circuitry, such as switches and clocking, the high precision is already built-in. Offset-related parameters such as Common-Mode Rejection (CMR) and Power-Supply Rejection (PSR) are frequently at high levels of 120 dB (1µV/V) or better for the Zero-Drift amplifier.

Taking a brief look back at the evolution of the 'Zero-Drift' amplifier shows how far they have come. The earlier Auto-Zero operational amplifiers came in non-standard packages, as they required external capacitors to dial in the overall performance. They also suffered from significant clock-frequency content in their output spectrum, which was often within the bandwidth of interest and, therefore, difficult to remove by filtering. A good step forward was made by introducing more sophisticated clocking schemes; for example, randomizing the chopping clock for the purpose of spreading out the clock tones over a wider bandwidth. One such model is the MCP6V01 from Microchip Technology Inc. This worked reasonably well, but with the downside of an overall increase in the op amps' noise floor, as will be discussed in more detail later.

The 'chopper-stabilised' amplifier
At this point, it seemed proven that the offset-related performance of an op amp could be successfully improved with the addition of digital self-correction circuitry. Some new product introductions aimed at ultra-low offset performance, and embraced the use of switches by combining the 'Auto-Zero' and the 'Chopper' topologies at the expense of power consumption and complexity. The complexity of such architectures can be a challenge for semiconductor manufacturing, and the attention shifted back on how to augment a time-continuous amplifier with a high level of precision. What resulted is one of the prevalent basic architectures of today's self-correcting amplifiers, the so-called 'Chopper-Stabilised' amplifier.

The principal architecture comprises two distinct amplifier signal paths connected in parallel – a 'Main' amplifier and an 'Auxiliary' amplifier (figure 1).

 Chopper-stabilised operational amplifier

Figure 1: Block diagram of a chopper-stabilised operational amplifier, consisting of two distinct paths—the higher-bandwidth, time-continuous path and the lower-bandwidth, chopper-amplifier path.

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