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Sleep easy with this desk fan speed minimiser

26 Dec 2014  | Michael Whybray

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Most desk fans I have come across offer three speeds: Full Speed, Almost Full Speed, and Off – useless if you want just a gentle air movement, and far too noisy if you are trying to get to sleep (in your bedroom of course, not at your work desk!). The squirrel cage induction motors they use have switches to two or more windings – and possibly a capacitor – to reduce the drive current. But unless the drive frequency is also reduced, the torque and speed stability are poor, so minimal speed reduction is usually available on these fans. Using a triac to provide phase control of the voltage works poorly for the same reason, with the speed very sensitive to the triac firing phase angle and fan load, and has a tendency to stall.

Far better speed stability is obtained by lowering the drive frequency from the standard 50Hz (or 60Hz). The main problem is how to do this without spending more than the fan itself cost! The design idea shown in figure 1 achieves this for a few dollars by using a triac to allow only every third half-cycle of the AC mains voltage through to the motor, as shown in figure 2.

Although not a continuous sine wave, the fundamental frequency can be seen to be 1/3 of the original mains frequency (60ms per complete cycle rather than 20ms), and it drives the motor with smooth impulses of regular spacing and opposite polarity, which keep the motor's internal magnetic field, and hence the rotor, rotating nicely. The result is stable fan operation at a nice low speed which is very much quieter. The usual fan speed control switch settings now have little effect, as the lower drive frequency is the dominant influence on speed.

 Motorspeed controller

Figure 1: Motorspeed controller.

Looking at figure 1, R1, D1, D2 and C4 rectify and smooth the incoming 240VAC mains to provide a low current -5V supply for the two standard logic circuits: a CD4070B Quad XOR, and a 74HCT191 4-bit counter. The 240V mains is also fed via R2 to the first XOR gate (wired as a non-inverting buffer) which clips it at -5.6V and +0.6V using the built-in input protection circuitry of the IC, then does an almost zero-crossing detection, resulting in a square wave clock at mains frequency. C1 & R2 filter out mains noise and create a time lag about of about 0.4ms for the clock signal compared to the incoming mains waveform. C2 provides 1V of dynamic hysteresis over the gate to ensure clean switching, and to reject glitches on the mains and -5V rail as the triac is triggered.

The clock signal passes through the second XOR buffer stage, which together with its output capacitor C3, provides a delay of about 500ns. Presenting this with the original clock signal to the inputs of the third XOR gate results in a short positive output pulse every time the incoming clock signal transitions high or low, so we now have a pulse 0.4ms after every zero-crossing of the mains signal, i.e., every 10ms (incidentally, a virtue of the venerable 4000-series logic circuits is that you can take liberties like loading the output with a capacitor, as the transistor channel resistance limits the current to a safe value if the supply is under 10V or so – see page 3 of 4000 Series Logic and Analog Circuitry).

The short positive pulses go to the clock input (CP) of the 74HCT191 binary counter. This is configured to count down (one step every 10ms) from its Parallel Load value to zero. On reaching zero, the Terminal Count (TC) pin goes high, and causes the voltage across C5 to rise as current flows through R3. On reaching 2.5V (after about 0.3ms), the output of the final XOR gate (in this case an inverter) drives counter Parallel Load input /PL low, forcing a load of the data '0011' on inputs D3-D0. This immediately sets TC low again. The result is that the counter cycles through: 0011, 0010, 0001, and then via a brief visit to 0000, back to 0011.

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