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Software promises faster design closure with Arria 10 FPGAs

18 Dec 2014

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Altera Corp. has introduced its Quartus II software v14.1 that boasts additional support for Arria 10 FPGAs and SoCs, which the company claims as the FPGA industry's only devices with hardened floating point DSP blocks and the industry's only 20nm SoC FPGAs that incorporate ARM processors. The latest software allows users to choose among three unique DSP design entry flows and achieve up to 1.5 TFLOPS of DSP performance. The solution also provides several optimisations that enhance designer productivity by reducing design time of Arria 10 FPGAs and SoCs, added Altera.

Integrated IEEE 754-compliant, floating-point DSP blocks in Arria 10 FPGAs and SoCs deliver unparalleled levels of DSP performance, designer productivity and logic efficiency. The Quartus II software v14.1 offers an advanced tool flow with multiple design entry options that target the hardened floating point DSP blocks and allow users to quickly design and deploy solutions that address a range of computationally intensive applications, in areas such as high-performance computing (HPC), radar and medical imaging. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers. Unlike a soft implementation, hardened floating point DSP blocks do not consume valuable logic resources for floating point operations.

Arria 10 FPGAs, SoC

The Quartus II Software v14.1 features an enhanced Design Space Explorer II (DSE II) tool for faster timing closure, which delivers real-time status and reporting data to users. The data can be used to do side-by-side comparisons of multiple compiles being generated simultaneously on compute farms. The software also has an optimised centralised IP catalogue and improved graphical user interface (GUI) that helps to store and easily find all custom IP in a single location.

Additional support is also offered for Altera's non-volatile MAX 10 FPGAs, which feature dual-configuration flash, analogue and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device. Likewise, enhancements to the JNEye serial link analysis tool further simplify board-level design and planning. The JNEye tool, along with Arria 10 silicon models, is able to simulate transmission line models and estimate insertion loss and cross talk parameters in Arria 10 designs.

Both the Subscription Edition and the free Web Edition of Quartus II software v14.1 are now available for download. Altera's software subscription program consolidates software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition, and a full license to the IP Base Suite, which includes Altera's most popular IP cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.

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