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CMC unveils additional Spice model standards for SOI devices

29 Dec 2014  | Keith Green

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The Compact Model Coalition (CMC) has unleashed a number of additional models for SOI devices and revealed its plans to work on GaN HEMT Spice model standards. Previously known as the Compact Model Council, CMC aims to unveil more standards and make model codes of several existing standards available to the public.

New models called BSIM-IMG and HiSIM-SOTB were developed for extremely thin-body SOI CMOS (ETSOI) and will enhance the popular BSIM and HiSIM standards platforms. This technology is gaining significance as an option for advanced, scaled CMOS.

Additionally, the CMC has made all of its Verilog-A model equation codes available. These models were previously only available to members, but now can be downloaded by anyone from the CMC's website. They include modern model equation sets for MOS capacitors (or varactors), two- and three-terminal resistors, and junction diodes.

Now users can customise the model equations within the Verilog-A codes. Such customisation is useful for modelling MEMs devices, sensors, memory elements and power transistors.

The recent ETSOI models were developed by researchers at The University of California at Berkeley (BSIM-IMG) and Hiroshima University (HiSIM-SOTB), and have been extensively tested using data provided by CMC members. Simulation convergence and runtime were also evaluated to ensure robust usability in circuit design.

Looking forward, the CMC plans to add reverse recovery to its junction diode standard, which will make it more useful for modelling power diodes and transistors. It also will introduce additional GaN HEMT Spice model standards including power HEMTs and RF HEMTs, with or without gate isolation, enhancement mode, or depletion mode.

Many traditional silicon companies are now developing and/or designing with GaN HEMTs. Additionally, some specialised GaN HEMT companies recently joined the CMC to assist with this project.

CMC model standards

The CMC has been developing modelling standards for nearly two decades.

The CMC, whose members include more than 40 companies, also has standards for planar bulk CMOS, FinFETs, partially depleted SOI CMOS, SiGe HBTs and LDMOS. Members include Altera, Broadcom, Cadence, GlobalFoundries, IBM, Intel, Keysight, Mentor Graphics, Micron, Qualcomm, Samsung, Synopsys, Texas Instruments and TSMC.

Membership is open to any semiconductor company by contacting the Si2 staff. Benefits include early access to model codes and the opportunity to collaborate on standards with experts. Modelling and simulation experts collaborate with a common goal of reducing IC design cost and enabling faster time-to-market by improving design simulation accuracy and operability.

As a team, modelling and simulation experts from semiconductor foundries, EDA companies, circuit design companies and academia collaborate with a common goal of reducing IC design cost and enabling faster time-to-market by improving design simulation accuracy and operability.

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