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How to gate clock pulse train without truncating

22 Jan 2015  | Viktor Safronov

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To gate an integral clock pulse sequence from a continuous source without distorting pulse duration and number is not a trivial task. In most cases, a simple AND gate will cause problems (figure 1).

Clock pulses pass through the AND gate as long as the asynchronous strobe E is high. If loss or distortion of even one pulse is critical, then the simple AND gate is unsuitable, as the first and the last pulse in the burst will often be distorted (shorter than usual pulse) due to the lack of synchronization between clock and E.

This design idea demonstrates a mathematical approach to synthesize an asynchronous gated circuit able to gate an accurate pulse train from a clock signal without distorting pulse duration. Such circuits are called quantizers.

Figure 1: Two ways of gating pulse train, using gate signal E and an AND gate (Y output), or a quantizer (blue).

Let's make a state transition table based on the operational principle of a quantizer:

Figure 2: Asynchronous finite-state machine (FSM) transition primary table, where 1,2,3,4,5,6,7, the numbers of stable FSM states, are circled (G is the clock input)

Using figure 2, let's make final pairs tables according to Mealy and Moore:

Figure 3: Final pairs tables by Mealy (left) and Moore (right), where: MC1: 2-5-6-7 and MC2: 1-3-4 are maximum compatible sets (by Mealy); MC1: 5-7, MC2: 1-2-6 and MC3: 1-3-4 are maximum compatible sets (by Moore).

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