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Designing envelope tracking modulator

12 Feb 2015  | Peter Markowski

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The stepping output pattern of the multi-level converter creates high-frequency harmonics, which are reflected in the RF signal. The 16 subconverters used for the envelope tracking design allowed the frequency of this noise to be shifted far away from the RF channel, where it can be handled much more easily. In some applications, satisfactory operation may be achieved without any LC filter whatsoever. In other situations, more than 16 cells or subconverters with fractional amplitudes may be used instead of the filter.

Altera FPGA custom controller
A custom controller was developed in an Altera Cyclone FPGA. The initial design, similar to the one used in common multi-level converters, was based on 16 equally phase-shifted digital sawtooth waveforms and comparators. See figure 6, which provides an example with only four phases shown to avoid cluttering the picture, but the principle for 16 phases is the same.

Figure 6: Simple realisation of the PWM sequence for a low-voltage multi-level converter. The phase shift between the sawtooth and the input signal creates a variation in the step pattern.

This structure can be very easily implemented in an FPGA using Simulink and DSPBuilder.

Figure 7: Simulink / DSPBuilder implementation of a 16-phase PWM generator. The initial value of each counter produces the desired phase shift.

Careful analysis of the performance of the converter based on this controller revealed a relatively high level of completely random noise. This would be irrelevant for DC/DC applications, as this noise would be completely suppressed by the low-frequency output filter. For envelope tracking, with almost no output filtering, this noise was unacceptable. It turned out that the source of this random behaviour was an uncontrolled phase relationship between the command signal and sawtooth generators. To understand this, see figure 6, where identical sinusoidal input leads to significantly different step patterns, illustrating how the peak of the sine wave relates to phase relationships of the sawtooth pattern. The underlying base band component is nearly identical, but harmonic content cannot be filtered out by using a large LC filter, as this would kill the bandwidth.

As some of the harmonic content becomes now unpredictable, so too is its resulting impact on the RF signal. This makes a difference because only predictable (deterministic) voltage ripple can be compensated by digital pre-distortion (DPD), which is commonly used in today systems.

Figure 8: Deterministic PWM pattern achieved by synchronising the counters with the command signal. All counters increment simultaneously by one step only when the command signal is decreased in a given clock period.

This random component was completely eliminated by a simple modification of the overall PWM generator. Instead of having all sawtooth counters free running, we now made them enabled always and only when the input signal commands "step down" in the multi-level pattern (figure 8). In this way independent dynamics of the sawtooth generator were eliminated and this, in turn, eliminated random components of the multi-level pattern.

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