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Functional safety design flow from Lattice now available

26 Feb 2015

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The Functional Safety Design Flow solution, which enables users to bring their product to market faster, is now available per Lattice Semiconductor. In addition, it is certified by TÜV-Rheinland, an independent organisation recognised for safety and quality testing.

"By using Lattice's qualified Functional Safety Design Flow, designers can adhere to the latest safety design methodology when developing safety-critical designs, accelerate their certification process and reduce design costs", said Jim Tavacoli, senior director, Product and Segment Marketing, Lattice.

IEC61508 has become the global standard for functional safety certification, and many industry specific standards are derived from it. The Lattice solution comprises a design flow and the development tools necessary to ensure that applications comply up to Safety Integrity level 3 (SIL3) certification. The Functional Safety Design Flow solution includes: Lattice Diamond Design Tools suite (a complete design and verification flow including Lattice Synthesis Engine and incorporating third party tools such as Aldec Active-HDL simulator and Synopsys Synplify Pro synthesis) and Safety User Manual. Lattice FPGA families covered include both non-volatile (MachXO, MachXO2, LatticeXP2) and SRAM-based (LatticeECP2, LatticeECP2M & LatticeECP3) products.

Highlights:

  • Speed IEC61508 Certification for safety-critical applications
  • FPGA Functional Safety Design Flow certified by TÜV Rheinland
  • Adhere to latest safety design methodology, save time, reduce costs
  • Supports MachXO, MachXO2, LatticeECP3 & other Lattice FPGA families



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