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Imperas unveils open virtual platforms to MIPS Warrior CPU

26 Feb 2015

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Imperas is introducing its Open Virtual Platforms (OVP) processor models for the MIPS Warrior P-class and M-class CPU IP cores from Imagination Technologies. It also announces the release of example virtual platforms, support for the cores in the Imperas Multicore Software Development Kit (M*SDK), as well as support for Imagination Codescape Debugger in the Imperas M*SDK and M*DEV.

The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS. The models of the P5600 and M51xx processor cores, as well as models of other MIPS processors, work with the Imperas and OVP simulators, including the QuantumLeap parallel simulation accelerator, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

"Partnering with Imperas to provide models in their innovative virtual platform tools provides a huge advantage to users of MIPS Warrior CPUs. These models, together with Imperas' new EPKs that let users run high-speed simulations of MIPS-based systems-on-chips on any suitable PC—can benefit MIPS customers and anyone developing software for MIPS platforms," said John Min, director of processor technology marketing for Imagination. "It is an additional benefit to our users to enable them to use the Codescape debugger for software development on both virtual platforms and hardware platforms."

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software engineers to have a development environment available early to accelerate the entire product development cycle. Virtual platforms utilising these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP processor models.

The OVP models also work with the Imperas advanced tools for multi-core software verification, analysis and debug, including key tools for hardware-dependent software development such as OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis. The tools utilise the Imperas SlipStreamer patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

"MIPS CPUs, with state of the art features such as multi-threading and hardware virtualisation, require state of the art software development tools," said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative. "OVP Fast Processor Models, which are faster and easier to use than other models, accelerate the development cycle and make software debug, test and optimisation easier for software engineers."

OVP offers developers models of all MIPS processor cores, including the MIPS Aptiv cores and the MIPS Classic cores—with MIPS Warrior core support now rolling out. OVP also has the new Extendable Platform Kits (EPKs) from Imperas, which are virtual platforms (simulation models) of the target devices, including the processor model(s) for the target device plus enough peripheral models to boot an operating system or run bare metal applications. The platform and the peripheral models included in the EPKs are open source, so that users can easily add new models to the platform as well as modify the existing models.




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