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PIC MCUs offer up to two independent closed loop channels

27 Feb 2015

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Microchip Technology Inc. has introduced a line-up of 8bit PIC MCUs with the release of the PIC16(L)F1769 family, which, according to the company, is the first PIC MCU devices to provide up to two independent closed loop channels. This is achieved with the addition of the Programmable Ramp Generator (PRG) that automates slope and ramp compensation, boosts stability and efficiencies in hybrid power conversion applications.

PIC16(L)F1769

The PRG provides real-time, down to the nanosecond, responses to a system change, without CPU interaction for multiple independent power channels. This allows customers the ability to reduce latency and component counts while improving system efficiency.

The PIC16(L)F1769 family includes intelligent analogue and digital peripherals, including tri-state op amps, 10bit ADCs, 5bit and 10bit DACs, 10bit and 16bit PWMs, and high-speed comparators, along with two 100mA high current I/Os. The combination of these integrated peripherals help support the demands of multiple independent closed-loop power channels and system management, while providing an 8bit platform that simplifies design, enables higher efficiency and increases performance while helping eliminate many discrete components in power-conversion systems, Microchip stated.

In addition to power-conversion peripherals, the PIC MCUs have a unique hardware-based LED dimming control function enabled by the interconnections of the data signal modulator (DSM), op amp and 16bit PWM. The combination of these peripherals creates a LED-dimming engine synchronising switching control eliminating LED current overshoot and decay. The synchronisation of the output switching helps smooth dimming, minimises colour shifting, increases LED life and reduces heat. This family also includes core independent peripherals (CIPs) such as the configurable logic cell (CLC), complementary output generator (COG) and zero cross detect (ZCD). These CIPs take 8bit PIC MCU performance to a new level, as they are designed to handle tasks with no code or supervision from the CPU to maintain operation, after initial configuration.

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