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Soft IP core addresses interface needs for I2C designs

06 Mar 2015

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Digital Core Design (DCD) has announced a soft IP core geared for I2C designs. According to the company, the DI2CM core offers an interface between a microprocessor or MCU and the I2C bus. It can work as a master transmitter or master receiver, depending on a working mode, determined by the MCU, stated DCD.

This universal solution is available with various system interface wrappers such as AMBA-APB bus, Altera Avalon bus and Xilinx OPB bus.

DI2CM core

Saying that the I2C is a two-wire, bi-directional serial bus, which provides simple and efficient method of short distance data transmission between many devices, is quite obvious. But still, reality shows that the I2C bus can be very confusing, and not only for the newcomers.

The DI2CM core incorporates all features required by the latest I2C specification, said Piotr Kandora, R&D director at DCD. This includes clock synchronisation, clock stretch, arbitration, multi-master systems and high-speed transmission mode. The DI2CM IP core has also been equipped with built-in 8bit timer, which allows operation for a range of data transfers speeds.

DCD's latest solution is a technology independent design, that's why like all other company's IP cores, it can be implemented in a variety of process technologies. It conforms to the latest I2C specification and offers support for both 7bit and 10bit addressing formats on the I2C bus. In addition, it is fully synthesisable, has a static synchronous design, and flaunts positive edge clocking and no internal tri-states. It is also scan test ready.




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