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FinFET transistors adoption grows steadily in foundries

13 Mar 2015  | Arvind Narayanan

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FinFET transistors have been widely adopted at major foundries and their adoption has been growing at a steady pace as they offer power, performance and area that planar transistors cannot provide. Because of this, manufacturers prefer them in assembly of products that require long battery life and performance such as smartphones and tablets.

When Intel first used FinFETs at the 22nm node, they claimed 37 per cent better performance (at the same total power) or 50 per cent power reduction (at the same speed) than bulk, PDSOI or FDSOI. These numbers are compelling and continue to improve even down to 14nm, and presumably, beyond.

In terms of power usage, controlling power leakage has been a huge challenge for planar devices, especially at smaller nodes. By raising the channel and wrapping the gate around it, FinFETs create a fully depleted channel to overcome the leakage problems of planar transistors. The better channel control of FinFETs leads to lower threshold and supply voltages.


FinFET performance, power and area advantages. (Source: TSMC)

While leakage is under control in FinFETs, dynamic power consumption accounts for a significant chunk of the total power. FinFETs have higher pin capacitances compared to planar transistors, which results in higher dynamic power numbers. According to Cavium Networks, "FinFETs bring a 66 per cent increase in gate capacitance per micron compared to 28nm process, and at the same level of the 130nm planar node."

FinFET gate capacitance

FinFET gate capacitance compared to planar processes. (Source: Cavium Networks)

So what does this mean to the design engineer and how does it change the design flow from an implementation perspective? Dynamic (a.k.a. switching) power needs to become a cost function during optimisation and has to be considered at all the stages of the flow.

FinFETs add to the complexity of physical design flow. Tighter design rules and FinFET process requirements, such as voltage threshold-aware spacing, implant layer rules, etc., impose restrictions on synthesis, placement, floor planning and optimisation engines that directly impact design metrics. And because FinFETs are being implemented at 16/14nm, multi-patterning automatically becomes a part of any design using FinFETs, which adds yet another layer of complexity.

Design automation technologies for FinFETs need to be finFET-aware to reduce switching power and offer capabilities such as power-aware RTL synthesis, activity-driven placement and optimisation, CTS (clock tree synthesis) power reduction, and concurrent optimisation of both dynamic and leakage. Power optimisation needs to start early in the design flow and the architecture selection needs to be power friendly to ensure lowest power when the design is realised.

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