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Verification IP for MIPI SoundWire streamlines system design

17 Mar 2015

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Synopsys Inc. has recently unveiled a verification IP (VIP) for the MIPI Alliance SoundWireSM1.0 specification. According to the company, the VIP for MIPI Sound Wire is based on a native System Verilog UVM architecture to enable IP, subsystem and SoC designers to optimise their designs and accelerate verification performance.

Synopsys VIP for MIPI SoundWire also includes System Verilog source code test suites to eliminate the tasks of developing a verification environment and the required tests. Complete with verification plans, built-in coverage and support for protocol-aware debug, Synopsys VIP for MIPI SoundWire accelerates verification closure for designers of low power audio and control interfaces used in mobile and mobile-influenced devices.

"MIPI Sound Wire consolidates many of the key attributes available in mobile and PC industry audio interfaces and introduces a scalable, low power, two-pin multi-drop architecture that can be used to transport multiple audio streams along with embedded controls and commands," said Joel Huloux, chair of the board of MIPI Alliance. "The release of Synopsys VIP for MIPI Sound Wire strengthens the ecosystem, required to facilitate early adoption and fast development of MIPI Sound Wire-based designs."

Synopsys VIP for MIPI SoundWire is available standalone as well as being included in the Synopsys VIP Library and the Verification Compiler products.




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