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Addressing pre-silicon emulation challenges

25 Mar 2015  | Neha Srivastava, Saloni Raina, Akshay Bisht

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The only way out of such a situation is to either have a new model, or discount the erroneous assertion of these signals( if verification and mixed signal simulation results give confidence), as they are purely driven from model and do not have any RTL logic in the path.

b) Data loaded to a particular flash block getting reflected at some other location

Typically, this example shows a situation where flash block assignments are different for the emulation model and the DUT. As a result of this, Data loaded into flash block-1 16k low region was reflected at block -2 when read by RTL path:

Explanation: The SoC which was being ported to emulator had 6 low 16k regions as shown below:

However the flash emulator model which was present at emulator had only 4 such regions and alignment of flash blocks in emulator model was different. A look below:

So the code which was intended for 1st low 16Kb block was loaded to block-2. Consider the simulation snippet from the Verification environment, where the flash block assignment was in accordance with the design.

Snippet from simulation environment flash:

When code execution was tried on emulation, only garbage data (shown below) was sent by flash as access was made to a block which was correct from SoC Flash architecture perspective but was incorrect from Emulator flash model side.

Snippet from emulation environment flash:

The resolution in this particular situation was that the code intended for 5th and 6th block had to be omitted as it was not possible to load it into smaller flash. By adjusting address offsets flash block loading issues could be managed.

1. Testing on Emulation platform can be done in 2 ways. One is to map the entire chip design onto the emulation platform which requires a relatively large capacity. Other approach can be to map smaller sub-systems of the design onto emulation such that the platform can be shared amongst multiple projects. Based on the requirements, the project builds should be created and this expensive resource should be intelligently allocated.

2. In normal LA mode(Logic analyser mode) timing sensitive dynamic targets are connected, and clocks can't be stopped. In this case it is easy to miss point of failure as discussed earlier. But there is also an option of the less explored STB mode. Static Target TestBench (STB) mode is used for emulating with a static target (that allows stopping and restarting the clock), or without a target system connection. In STB mode, FV(Full Vision) and FVDT(Full Vision Deep Trace) support incremental upload. You can mix run and trigger operations, add more probes, and upload probes. Thus, STB mode can be used for multiple trace uploads helping solve out the problem of failure point miss.

3. It is extremely important to have a well-defined Pre-Silicon Test Plan which is intelligently drafted complementary to the SoC Verification Plan to have an effective coverage of scenarios that can't be covered in verification due to speed limitations. The only way to use Emulation platform effectively is by having a well defined Test plan keeping the strengths and weaknesses of this platform into consideration.

4. Introduction of breaknets unknown to the users can be avoided by the following:

 • Putting a user defined breaknet earlier in the path- so that compiler doesn't put its own!
 • Simplify combinational logic—so that there is no requirement of a breaknet.
5. There is a requirement to put in additional efforts during the bring up phase of a new project to decide on the reuse and specification compliance of the models to be used. Learning from previous experiences plays a key role.

About the authors
Neha Srivastava is lead design engineer, while Saloni Raina and Akshay Bisht are both design engineers. They are with Freescale Semiconductor (India).

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