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Package Integrator suite optimises IC-package-board design

25 Mar 2015

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Mentor Graphics revealed its Xpedition Package Integrator flow, which automates planning, assembly and optimisation of multi-die packages. The Package Integrator suite provides designers guidance and easy-to-use tools for prototyping.

This solution ensures that ICs, packages and PCBs are optimised with each other to reduce package substrate and printed circuit board (PCB) costs by efficient layer reduction, optimised interconnect paths and streamlined/automated control of the design process. The Xpedition Package Integrator product also provides formal flow for ball grid array (BGA) ball-map planning and optimisation based on an "intelligent pin" concept, defined by user rules. In addition, multi-mode connectivity management system (incorporating hardware description language (HDL), spreadsheet and graphical schematic provides cross-domain pin-mapping and system level cross-domain logical verification.


Additional features include cross-domain interconnect visualisation in a single view; powerful, comprehensive and user-friendly multi-mode physical layout tools with industry leading routing for PCB, MCM, SiP, RF, Hybrid and BGA designs; and fully automated library development.

The Xpedition Package Integrator flow leverages other Mentor Graphics tools such as the HyperLynx signal and power integrity product, FloTHERM computational fluid dynamics (CFD) thermal modelling tools, and the Valor NPI substrate fabrication checking tool. To complete the Mentor Graphics co-design solution, Nimbic was acquired in 2014. The Nimbic technology provides Maxwell-accurate, 3D full-wave electromagnetic (EM) high-performance simulation solutions that accurately calculate complex electromagnetic fields for chip-package-board simulation.

"The Xpedition Package Integrator design flow, especially the unique virtual die model, gives package and board design experts meaningful guidance and tools for their parts of the system design efforts," said Herb Reiter, president of eda2asic and director of 3D-IC Programs at Si2. "This flow also allows quick and structured feedback to the IC designers and enables true die-package-board co-design and optimisation towards best possible performance versus power ratios for your next system design."

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