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MIPI subsystem speeds product roll-out

02 Apr 2015

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Faraday Technology Corp. has unveiled its MIPI subsystem of Camera Serial Interface (CSI-2) and low-voltage differential signaling (LVDS) in UMC's 40nm LP process that claim to address the requirements of quality and cost within the competitive schedule for applications of Internet of Things (IoT), mobiles and cameras such as wearable and mobile devices, digital still camera (DSC), surveillance, automotive and medical devices.

Faraday's MIPI subsystem includes composite IP (Co-IP), the prototype and system loopback testing. The silicon-proven Co-IP integrates combo PHY IP, MIPI CSI-2 RX controller and LDVS controller. It is configurable for various sensor interfaces of MIPI, LVDS, sub-LVDS and HiSPi, supporting the transmission speed up to 1Gb/s for each of four data lanes. The prototype (combo PHY EVB and controller FPGA code) assists customers in creating their platforms and bringing system-level development and verification forward to the pre-silicon stage. In addition, the at-speed system loopback testing ensures mass production quality with a lower cost.

"Through close collaboration with lead-edge SoC customers, we saw increasing MIPI adoption in various applications beyond the mobile market," said Jensen Yen, associate VP of marketing and spokesperson at Faraday. "Faraday's flexible MIPI subsystem can accelerate customers' product creations to satisfy differential requirements in the market. It has been adopted by some of our customers in the multimedia field and enabled quicker tape-outs than they expected, including a leading surveillance vendor. In addition to MIPI, Faraday will continue development in other IP subsystems for more application fields."




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