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Developing correct-by-design PCBs

08 Apr 2015  | Minoru Ishikawa

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As both chip and board complexities continue to spiral upwards, the number of challenges faced by designers grows increasingly as well. The proliferation of multi-Gbps differential signals, for example, brings with it the need for tightly length-matched routing and restrictions on the use of vias. Extensive simulation to characterise these busses, including long bit streams to validate performance down to very low bit error rate (BER levels), is necessary to ensure adequate system margins. This requirement is no longer unique to high-speed serial links, but has now spread to single-ended, parallel links like DDR4. PCBs have to be tested for signal integrity, power integrity, and radiated emissions, in order to ensure that the design works correctly before the first prototype is even built.

As such, designing a modern, high-speed PCB is a pretty daunting task. It requires high levels of expertise in a number of different areas. Infusing that expertise into the design process, however, can be made more practical through the use of rules-based verification.

Electrical signoff glow
In many companies, the needs of a high-speed PCB are met by employing simulations both before and after the PCB layout process. Adding a concurrent verification process to the layout phase not only improves the quality of the design, but also identifies problems early when they are easier to rectify. Combining simulation with rules-based verification allows for a more comprehensive characterisation of the electrical performance of the board, and can be considered as being an "Electrical Sign-Off,"or ESO.

Figure 1 illustrates an ideal ESO flow. Layout constraints can be determined using analysis prior to routing. During the layout process, a design rule-checking tool ensures that design rules are not violated while the layout progresses. Finally, post-layout signal integrity and power integrity simulations can be run to ensure that the final design has no errors before releasing the board to manufacturing.

Figure 1: The electrical signoff flow.

Concurrent verification during layout
Every design requires that a set of constraints be developed during each phase of the project.

Floorplanning constraints are essential for a number of reasons involving several disciplines. For example, certain components may need to be placed close together to ensure timing margins are met or loss budgets are not exceeded. If terminations are used on a signal, these termination components need to be placed close to a driver or receiver to be effective. Decoupling capacitors need to be placed as close to an IC as possible to limit the inductance between the capacitor and the power pins of the IC. Mechanical constraints on placement, including placement interferences or heating concerns, must also be considered when doing floorplanning.

As critical nets are routed, they must conform to requirements set by the electrical constraints. They must not exceed maximum length limits. Signals often have to be tightly length-matched to other signals. They must not be routed with an excessive number of vias. They must be routed with certain widths and above solid reference planes so as to maintain a consistent characteristic impedance. They must not be routed too close together to alleviate crosstalk concerns.

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